Clock Phase Alignment Using Delay Control Across Core Domains
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Solution Overview
Problem
In multiple core systems, independent clock signals for each core and memory components require synchronization to facilitate effective data communication, but existing methods like asynchronous FIFO devices and phase locked loops are inefficient and difficult to mass-produce, especially under dynamic voltage frequency scaling conditions.
Innovation Solution
A device comprising a phase detector, delay generator, and controller aligns phases of clock signals by generating preceding and succeeding signals, determining phase relationships, and adjusting clock gating to synchronize clock signals, allowing for efficient data communication between domains with different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFO devices or phase locked loops are used to synchronize clock signals, then data communication between clock domains can be achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the essential synchronization function from complex existing devices (asynchronous FIFO and PLL) by using only a phase detector and simple delay elements. This removes unnecessary complexity while retaining the core capability of synchronizing clock signals between domains.
Solution Approach 2:
Instead of using complex PLL circuits to generate synchronized clocks, the patent creates a simplified copy of the clock signal relationship by detecting phase differences and applying simple delay adjustments, achieving synchronization without replicating the complex PLL architecture.
2Reliability
If traditional synchronization methods are used, then clock signal alignment can be achieved, but adaptability to dynamic voltage frequency scaling is poor
Solution Approach 1:
The patent implements dynamic adaptability by continuously monitoring phase relationships and adjusting delay values in real-time based on detected phase differences. This dynamic adjustment mechanism allows the synchronization system to adapt to changing voltage and frequency conditions without requiring redesign or complex control circuits.
Solution Approach 2:
The phase detector provides continuous feedback about the phase relationship between clock signals, enabling the system to automatically adjust delay values to maintain synchronization under varying operating conditions including dynamic voltage frequency scaling.
3Manufacturing precision
If phase detection and delay adjustment are implemented, then clock phase alignment is achieved, but data transmission delays are reduced
Solution Approach 1:
The system performs preliminary phase detection and calculates the required delay adjustment before data transmission occurs. By pre-aligning the clock phases and establishing the correct timing relationship in advance, the system eliminates unnecessary waiting and setup delays during actual data transfer operations.
Data Source
AI summary
In a method and device to align phases of a first clock signal and a second clock signal, include a phase detector, a delay generator, and a controller. The phase detector is configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal. The delay generator is configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal. The controller is configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector.