Clock Phase Converter Using Selectable Delay Paths
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Solution Overview
Problem
Existing clock phase converters face challenges in generating a converted clock signal with a desired amount of delay while minimizing semiconductor circuit area and preventing the generated signal from exceeding one cycle of the clock signal, often requiring an increasing number of inverters which leads to inefficiencies.
Innovation Solution
A clock phase converter that includes a delayed clock signal generation unit, storage unit, logic combination units, encoder, divider, and multiplexer to select and output a delayed clock signal with a preset value, allowing for precise phase and frequency conversion by detecting the clock signal transition and sequentially delaying it.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of inverters is increased to adjust phase delay time, then the phase delay resolution is improved, but the semiconductor circuit area increases
Solution Approach 1:
The circuit divides the delay adjustment into discrete segments using individual switchable inverter paths. Each inverter stage represents a quantized delay unit, allowing precise phase control without requiring a continuous increase in total inverter count. The segmentation enables selective activation of delay stages based on required precision.
Solution Approach 2:
The circuit dynamically selects which inverter paths are active based on the required phase delay amount. Instead of having all inverters permanently connected in series, the design allows dynamic reconfiguration of the delay path length, optimizing the balance between delay precision and area usage for different operating conditions.
2Manufacturing precision
If the number of inverters is increased to achieve desired delay, then the delay precision is improved, but the generated clock signal may exceed one cycle of the input clock
Solution Approach 1:
The circuit incorporates feedback mechanisms through the controller that monitors the delay amount and adjusts the selection of inverter paths accordingly. This feedback control ensures that the total delay remains within acceptable bounds that prevent the output clock from exceeding one cycle of the input clock, while still achieving the desired delay precision.
Solution Approach 2:
The design changes the effective delay parameter by selectively enabling or disabling specific inverter stages rather than permanently committing to a fixed number of inverters. This parameter adjustment allows the system to achieve precise delay control while maintaining the constraint that the output signal completes within one input clock cycle.
3Adaptability or versatility
If more inverters are used to adjust phase delay, then the delay control flexibility is improved, but the device complexity increases
Solution Approach 1:
The circuit design makes the inverter array multi-functional by allowing different combinations of inverters to be activated for different delay requirements. The same physical inverter structure serves multiple delay values, and the controller universally manages various delay scenarios without requiring dedicated circuitry for each delay amount, thus reducing overall complexity.
Solution Approach 2:
The controller pre-configures the optimal inverter path selection based on the required phase delay amount before the actual delay is applied. This preliminary action allows the system to prepare the appropriate delay configuration in advance, simplifying the real-time operation and reducing the complexity of dynamic switching during signal processing.
Data Source
AI summary
Disclosed are a clock phase converter and a phase converting method that can generate a converted clock signal with a desired amount of delay by selecting and outputting an output signal corresponding to a preset value among output signals of a plurality of delayed clock signal generators that detect the transition of a clock signal and generate delayed clock signals by sequentially delaying the clock signal by a certain period of time.