Clock Generating Circuit With Dual Delay-Line Phase Selection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor systems, the local variation during fabrication leads to phase differences and duty cycle changes in internal clock signals generated by clock generating circuits, affecting synchronization and data transmission between semiconductor apparatuses.
Innovation Solution
A clock generating circuit comprising multiple delay lines and a delay control circuit that monitors duty cycles to generate selection signals, allowing for the selection and mixing of delay clock signals to produce a stable output clock signal, thereby compensating for local variations and ensuring synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single delay line is used to generate internal clock signals, then the device complexity is reduced, but the phase accuracy and duty cycle stability deteriorate due to local fabrication variations
Solution Approach 1:
The patent divides the clock generation function into multiple parallel delay lines (first delay line and second delay line) instead of using a single delay line. Each delay line processes the input clock signal independently, and their outputs are combined through a selection circuit. This segmentation allows the system to compensate for local fabrication variations by selecting or combining outputs from multiple paths, thereby improving phase accuracy and duty cycle stability while managing device complexity.
Solution Approach 2:
The patent changes the operational parameters of the delay lines by introducing controllable delay amounts that can be adjusted independently for each delay line. The delay control circuit modifies the delay parameters based on monitoring feedback, allowing the system to optimize phase and duty cycle characteristics. This parameter adjustment capability enables compensation for fabrication variations without requiring identical physical structures.
2Manufacturing precision
If multiple delay lines are used to compensate for local variations, then the phase accuracy and duty cycle stability improve, but the device complexity increases
Solution Approach 1:
The patent merges the outputs of multiple delay lines through a selection circuit that combines the first delay clock signal and the second delay clock signal into a single output clock signal. This merging process allows the system to leverage the benefits of multiple parallel paths (improved accuracy) while presenting a unified output interface, thereby managing the complexity impact of having multiple delay lines.
Solution Approach 2:
The patent implements a feedback mechanism where the delay control circuit monitors the output clock signal characteristics (phase and duty cycle) and adjusts the delay control signals sent to each delay line accordingly. This closed-loop feedback allows the system to automatically compensate for fabrication variations and optimize performance, reducing the need for overly complex manual calibration or oversized safety margins in the delay line design.
3Adaptability or versatility
If the delay control circuit monitors and adjusts delay amounts dynamically, then the adaptability to fabrication variations improves, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent performs preliminary characterization of each delay line's characteristics (such as duty cycle and phase response) during the monitoring phase before normal operation. The delay control circuit stores these characterization results and uses them to pre-adjust the delay amounts, reducing the need for continuous dynamic adjustment during normal operation. This preliminary action reduces power consumption while maintaining adaptability to fabrication variations.
Data Source
AI summary
A clock generating circuit includes a first delay line, a second delay line, a selected phase mixing circuit and, a delay control circuit. The first delay line delays, based on a delay control signal, an input clock signal to generate a first delay clock signal. The second delay line delays, based on the delay control signal, the input clock signal to generate a second delay clock signal. The selected phase mixing circuit generates, based on a first selection signal and a second selection signal, an output clock signal from at least one between the first delay clock signal and the second delay clock signal. The delay control circuit monitors duty cycles of the first delay clock signal and the second delay clock signal to generate the first selection signal and the second selection signal thereby selecting at least one between the first delay line and the second delay line.