Clock Phase Detector Using Delayed Sampling for Variable Frequencies
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Solution Overview
Problem
Conventional synchronization techniques fail when clock frequencies vary due to changing power supply voltage levels, temperature, or programming, leading to increased complexity and latency in signal transmission between clock domains.
Innovation Solution
A high-resolution phase detector generates delayed versions of a first clock signal to sample a second clock signal, locating edge indications and computing phase and period values to synchronize signals across clock domains with varying frequencies, reducing latency and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous FIFOs are used to synchronize signals between clock domains with variable frequencies, then synchronization reliability is improved, but area overhead and latency increase significantly
Solution Approach 1:
The patent extracts the essential synchronization function from complex FIFO structures by using a simplified phase detector that only needs to detect phase relationships between clocks. The phase detector extracts phase information without requiring the full FIFO memory structure, thereby reducing area overhead while maintaining synchronization capability.
Solution Approach 2:
The patent creates a simplified model of the synchronization problem by using phase detection instead of full FIFO buffering. The phase detector creates a representative signal that captures the essential timing relationship between clocks, allowing synchronization without the overhead of copying and storing actual data through multiple clock domains.
2Reliability
If asynchronous FIFOs are used to synchronize signals between clock domains with variable frequencies, then synchronization reliability is improved, but latency increases due to multiple flip-flop stages
Solution Approach 1:
The patent extracts the critical timing information needed for synchronization without requiring data to pass through multiple FIFO stages. By detecting phase relationships directly, the system obtains synchronization information in a single clock cycle rather than waiting for Gray-coded pointer synchronization through multiple flip-flop stages.
Solution Approach 2:
The phase detector performs preliminary phase analysis between clocks before data transmission is required. This advance detection of phase relationships allows the system to prepare synchronization information in advance, eliminating the delay that would otherwise occur during actual data synchronization through FIFO structures.
3Device complexity
If conventional phase detection methods are used, then device complexity is reduced, but measurement precision of phase differences deteriorates
Solution Approach 1:
The patent segments the phase detection process into multiple discrete sampling points using delayed versions of the first clock signal. By sampling the second clock signal at multiple phase points throughout its cycle, the system achieves high-resolution phase measurement without requiring complex analog phase detection circuits.
Solution Approach 2:
The patent transitions from direct analog phase comparison to a time-domain sampling approach. Instead of measuring phase difference directly through complex analog circuits, the system uses multiple delayed clock samples to represent phase information in the time domain, achieving high precision through temporal resolution rather than spatial complexity.
Data Source
AI summary
A method and a system are provided for clock phase detection. A set of delayed versions of a first clock signal is generated. The set of delayed versions of the first clock is used to sample a second clock signal, producing a sequence of samples in a domain corresponding to the first clock signal. At least one edge indication is located within the sequence of samples.