Clock-Phase Adaptive Deserializer for Accurate Data Alignment
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Solution Overview
Problem
High-speed semiconductor systems require efficient data transmission schemes to handle high bandwidth data communication, but existing pre-fetch schemes struggle with aligning data correctly when internal clock signals have different phases, leading to errors in data alignment.
Innovation Solution
A deserializer is designed with a data aligner, selection signal generator, and selection output unit to align data using internal clock signals with different phases, generating higher and lower aligned data, and a phase detection signal to select the appropriate alignment based on the phase of the clock signals, ensuring accurate data alignment even when clock signals are inverted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pre-fetch schemes are used to achieve high data transmission rates, then bandwidth is improved, but data alignment accuracy deteriorates when internal clock signals have different phases
Solution Approach 1:
The system dynamically adapts to different clock signal phases by detecting the phase relationship between first and second internal clock signals and adjusting the data alignment accordingly. The deserializer can operate correctly whether the clock signals are in normal phase or inverted phase, making the system flexible and adaptive to varying clock conditions while maintaining high data transmission rates.
Solution Approach 2:
The invention changes the parameter of clock signal phase detection and adaptation. By detecting whether the second internal clock signal is in normal phase or inverted phase relative to the first internal clock signal, the system adjusts its data alignment strategy accordingly, ensuring accurate deserialization regardless of the clock phase relationship.
2Speed
If multi-phase clock signals are used to latch and output data in parallel, then data transmission speed is improved, but system complexity increases
Solution Approach 1:
The invention manages complexity by focusing on a specific parameter change - the phase relationship between two clock signals. Rather than complicating the system to handle all possible multi-phase scenarios, the deserializer detects and adapts to the specific phase relationship (normal or inverted) between the first and second internal clock signals, simplifying the overall system architecture while maintaining high-speed parallel data output capability.
Data Source
AI summary
Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.