Clock Phase Compensation for Supply-Droop Eye Margin Recovery
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Solution Overview
Problem
Supply droop-induced clock phase shifts cause significant eye margin loss in source-synchronous IOs with unmatched receiver (RX) clocking architectures, leading to reduced IO timing margin due to mismatched data and clock propagation delays.
Innovation Solution
An apparatus and method that compensates for supply droops by detecting voltage droops or rises using a droop detector, translating these into clock phase adjustments through a phase interpolator (PI) and/or delay locked loop (DLL), with a lookup table determining appropriate PI or DLL codes to maintain a trained relationship between the sampling clock strobe and data eye.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If unmatched receiver (RX) clocking architecture is used, then power consumption is reduced, but clock phase accuracy deteriorates due to supply droop-induced phase shifts
Solution Approach 1:
The patent implements a feedback mechanism where the receiver monitors incoming data edges and detects supply droop events. Based on this detection, the system dynamically adjusts the sampling clock phase to compensate for droop-induced shifts. This closed-loop feedback enables the unmatched RX architecture to maintain clock phase accuracy while preserving its power consumption advantages.
Solution Approach 2:
The patent changes the phase parameter of the sampling clock dynamically in response to detected supply droop conditions. By adjusting the clock phase offset based on real-time droop detection, the system compensates for timing shifts without requiring a complete architecture change, thus maintaining both low power consumption and high clock phase accuracy.
2Reliability
If supply voltage droop compensation is implemented, then eye margin is improved, but device complexity increases due to additional compensation circuits
Solution Approach 1:
The patent makes existing receiver components multi-functional by enabling them to perform both their primary functions and droop compensation functions. The same data sampling path is used for both normal data reception and droop detection, while the sampling clock generator is enhanced to provide both normal clocking and droop-compensated clocking. This universal approach improves eye margin without proportionally increasing device complexity.
Solution Approach 2:
The receiver performs self-compensation for supply droop by using its own internal resources. The droop detector leverages existing data edges and internal timing references to detect supply variations, and the phase adjustor uses the same clock distribution network to apply corrections. This self-service mechanism regains eye margin without requiring extensive external compensation hardware.
3Measurement precision
If clock phase adjustment is applied dynamically, then data sampling accuracy is improved, but processing time increases due to detection and adjustment overhead
Solution Approach 1:
The patent implements preliminary droop detection using data edges that are already present in the signal path. By detecting supply droop conditions early in the data sampling process and pre-adjusting the clock phase accordingly, the system compensates for timing shifts before they affect critical data sampling operations, thus improving accuracy without significant time penalty.
Solution Approach 2:
The patent maintains continuous data sampling operations while simultaneously performing droop detection and clock phase adjustment. The compensation mechanism operates continuously in the background without interrupting the primary data reception function, ensuring that data sampling accuracy is improved without introducing noticeable processing delays.
Data Source
AI summary
An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.