Low-Pass Filter Clock Circuit for Duty Cycle and Phase Correction
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Solution Overview
Problem
High-speed electronic circuits face challenges in maintaining an accurate 50% duty cycle and 180° relative phase offset for clock signals due to limited bandwidth of PCB traces, leading to phase offsets caused by trace length mismatches and sinusoidal waveform propagation.
Innovation Solution
A circuit employing self-referencing duty-cycle correction using serially-connected inverters, low-pass filters, and differential amplifiers to correct the duty cycle and phase offset of clock signals, incorporating switches and operational amplifiers for adaptive gain control and phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCB traces are used to distribute high-frequency clock signals, then clock signals can be transmitted to circuits, but the limited bandwidth of PCB traces causes phase offsets and duty cycle errors
Solution Approach 1:
The patent implements feedback by sampling the clock signal at multiple points through serially-connected inverters, filtering these samples with low-pass filters, and using a differential amplifier to compare and correct phase differences. The corrected signal is fed back to adjust the clock distribution, thereby compensating for PCB trace-induced phase offsets and duty cycle errors.
Solution Approach 2:
The patent introduces an intermediary correction circuit between the PCB trace and the destination circuit. This intermediary includes serially-connected inverters that sample the clock signal, low-pass filters that extract the fundamental frequency, and a differential amplifier that calculates and corrects phase differences, thereby mediating the harmful effects of PCB trace limitations.
2Ease of manufacture
If trace length mismatches occur in PCB layouts, then circuit layout flexibility is reduced, but phase offset correction becomes necessary
Solution Approach 1:
The correction circuit continuously monitors the clock signal phase through serially-connected inverters and uses a differential amplifier to detect phase differences caused by trace length mismatches. The feedback mechanism adjusts the clock signal to compensate for these mismatches, maintaining signal integrity despite PCB layout variations.
Solution Approach 2:
The patent changes the parameter being controlled from fixed trace length to dynamic phase correction. By using low-pass filters to extract the fundamental frequency and a differential amplifier to calculate phase differences, the system dynamically adjusts the clock signal parameters to compensate for trace length variations, thereby maintaining reliability despite manufacturing flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively corrects duty cycle and phase offset of clock signals, ensuring accurate clocking for high-speed applications like ADCs, even in the presence of trace mismatches and propagation effects.
Implementation Method 1
a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port
Implementation Method 2
a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters
Implementation Method 3
a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port
Data Source
AI summary
A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.