Precision Clock Module Phase Integrity Checking for GNSS Fault Isolation
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Solution Overview
Problem
High-precision clocks used in digital electronic equipment face challenges in identifying the source of faults between the main oscillator and the GNSS time reference, leading to potential instability and imprecision, with existing solutions being complex and costly or lacking a simple means for fault detection.
Innovation Solution
A clock module that includes a main precision oscillator and a second opportunity oscillator, along with processing means to measure and compare phase differences between the main oscillator, the GNSS reference, and the opportunity oscillator, calculating derivatives to detect failures and determine if the issue lies with the main oscillator or the time reference, using existing components without additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a GNSS receiver is used to control the main oscillator, then time reference accuracy is improved, but vulnerability to jamming and loss of locking increases
Solution Approach 1:
The patent introduces an intermediary integrity checking system that monitors the GNSS receiver and main oscillator interaction. This intermediary layer detects integrity issues (such as jamming or loss of locking) before they propagate to affect the clock output, allowing the system to switch to holdover mode proactively rather than reactively.
Solution Approach 2:
The integrity checking system performs preliminary detection of potential failures in the GNSS receiver or main oscillator before they cause time reference inaccuracies. By continuously monitoring phase differences and detecting anomalies early, the system can prepare for failure modes and switch to backup mechanisms preemptively.
2Reliability
If redundant oscillators are implemented to detect faults, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a self-service integrity checking mechanism where the existing GNSS receiver and main oscillator monitor each other through phase difference measurements. The system uses its own operational characteristics (phase relationships) to detect faults without requiring external test equipment or additional redundant oscillators, thereby maintaining reliability while avoiding increased complexity.
Solution Approach 2:
The integrity checking system continuously measures the phase difference between the GNSS receiver output and main oscillator, creating a feedback loop that detects anomalies. This feedback mechanism enables fault detection using existing system components rather than requiring separate monitoring hardware, thus improving reliability without proportionally increasing device complexity.
3Difficulty of detecting and measuring
If phase difference monitoring is implemented, then fault detection capability is improved, but processing complexity increases
Solution Approach 1:
The patent employs a computationally lightweight phase difference measurement approach that uses simple timing comparisons rather than complex analysis algorithms. The integrity checking relies on basic phase detection and threshold comparison, which are computationally inexpensive operations that can be performed continuously without burdening the system processor.
Data Source
AI summary
A clock module includes a main precision oscillator generating a first clock signal of a predetermined frequency, a receiving module receiving a time reference and providing a time reference signal controlling the main oscillator, and a detector for detecting a failure of the main oscillator or of the time reference signal. The detector includes: a second oscillator not controlled by the clock module and delivering a second clock signal of predetermined frequency; and a processor configured to measure a first phase difference between the first clock signal and the time reference signal, a second phase difference between the first clock signal and the second clock signal, and a third phase difference between the time reference signal and the second clock signal. The processor is configured to calculate calculating derivatives of the first order of the three phase differences measured so as to determine respective variations of the three phase differences.