Digital Clock Circuit for Phase-Synchronized Frequency Switching
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Solution Overview
Problem
Digital processing circuits in devices like wireless communications devices require variable reference clock frequencies to optimize signal processing, but existing solutions struggle to maintain phase synchronization when frequency shifts occur, leading to inefficiencies and potential loss of synchronization.
Innovation Solution
A reference clock generator with a programmable divider and phase adjuster that allows frequency changes while maintaining phase synchronization by adjusting the number of clock pulses, ensuring that the total number of pulses after a frequency shift equals those produced at the original frequency, thus maintaining synchronization with input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the reference clock frequency is changed to optimize signal processing for different modes, then processing efficiency is improved, but phase synchronization with input signals is lost
Solution Approach 1:
The patent implements a dynamic frequency selection mechanism that allows the reference clock generator to switch between different frequencies based on the current operating mode. The system dynamically adjusts the clock frequency to match the processing requirements of different signal types while incorporating phase tracking to maintain synchronization, thus resolving the contradiction between productivity improvement and reliability maintenance.
Solution Approach 2:
The system changes the clock frequency parameter according to the operating mode requirements. By implementing phase tracking that monitors and compensates for phase accumulation during frequency transitions, the system maintains synchronization reliability while allowing frequency parameter changes to optimize processing efficiency for different signal types.
2Reliability
If the reference clock frequency remains fixed, then phase synchronization is maintained, but processing efficiency for different signal types deteriorates
Solution Approach 1:
The patent implements a dynamic frequency selection mechanism that allows the reference clock generator to switch between different frequencies based on the current operating mode. The system dynamically adjusts the clock frequency to match the processing requirements of different signal types while incorporating phase tracking to maintain synchronization, thus resolving the contradiction between productivity improvement and reliability maintenance.
3Reliability
If pulse removal is implemented to maintain phase synchronization after frequency shifts, then synchronization is restored, but circuit complexity increases
Solution Approach 1:
The patent implements a feedback-based phase tracking mechanism that monitors the phase relationship between the clock signal and input signals. The phase tracker provides feedback information about phase accumulation during frequency transitions, enabling the system to determine when and how many pulses need to be removed. This feedback approach maintains synchronization reliability while avoiding the need for complex predetermined pulse removal logic.
Solution Approach 2:
The phase tracking mechanism automatically detects and compensates for phase shifts by monitoring the relationship between clock cycles and input signal cycles. The system self-adjusts by removing the appropriate number of pulses based on phase tracker feedback, eliminating the need for external complex control circuits and reducing overall system complexity.
Data Source
AI summary
A digital clock generation circuit (200) and method of operation (400). A digital clock (250) produces an output (220) with a first frequency or a second frequency. A clock control circuit (204, 206) selectively sets the digital clock (250) to produce either the first frequency or the second frequency. An excess pulse counter (212) determines a number of pulses produced by the digital clock (250) at the second frequency that differs in the number of pulses that would have been produced at the first frequency, had the clock frequency change to the second frequency not occurred. An output phase correction circuit (230, 232, 212) removes, in response to the digital clock (250) changing from producing the second frequency to producing the first frequency, the number of pulses from the output (220) that were counted by the excess pulse counter (212).