Clock Phase Generator for Early Late Sampling Clocks
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Solution Overview
Problem
Existing digital clock recovery systems struggle to generate clock signals with early or late transitions relative to ideal sampling points, which is necessary for optimal data recovery in digital communications, especially in threshold-based and classical Decision Feedback Equalization (DFE) implementations.
Innovation Solution
A clock phase generator that produces early or late sampling clocks by adjusting the phase separation between transition and data sampling clock signals, allowing for non-uniform spacing to optimize timing margins and jitter tolerance, using a delay mechanism that can be fixed or dynamic until predefined stopping criteria are met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If uniformly spaced transition and data sampling clock phases are generated using VCDL, then ideal data sampling at the center of the data eye is achieved, but the system cannot provide early or late sampling clocks needed for threshold-based DFE and classical DFE implementations
Solution Approach 1:
The clock phase generation is segmented into multiple independent delay elements that can be individually controlled. Each delay element can be adjusted to create different phase shifts, allowing the system to generate both uniformly spaced and non-uniformly spaced clock phases depending on the operational mode (ideal sampling, early sampling for threshold-based DFE, or late sampling for classical DFE).
Solution Approach 2:
The delay elements are made dynamically adjustable through control signals that modify their delay characteristics in real-time. This dynamic control allows the system to adapt the clock phase spacing according to different operational requirements, transitioning between uniform and non-uniform spacing without hardware reconfiguration.
2Reliability
If the data sampling position is moved earlier for threshold-based DFE, then optimal sampling for this equalization method is achieved, but the sampling occurs before the ideal center of the data eye
Solution Approach 1:
The system performs preliminary timing adjustment by advancing the data sampling clock phase before the ideal sampling point. This preliminary action is controlled by adjusting the delay elements to create an early clock phase, which is specifically required for threshold-based DFE operations where sampling must occur earlier in the bit period to account for intersymbol interference cancellation dynamics.
3Stability of the object's composition
If the data sampling position is delayed for classical DFE, then transients in ISI correction circuitry have time to settle, but the sampling occurs later than the ideal center of the data eye
Solution Approach 1:
The system performs preliminary timing adjustment by delaying the data sampling clock phase beyond the ideal sampling point. This preliminary delay is controlled by adjusting the delay elements to create a late clock phase, which allows transients in the ISI correction circuitry to settle before sampling occurs, specifically required for classical DFE implementations.
4Reliability
If non-uniform phase spacing is implemented to generate early or late clocks, then timing margins and jitter tolerance are optimized, but the uniform phase separation between transition and data sampling clocks is compromised
Solution Approach 1:
The phase separation between transition and data sampling clocks is made dynamically adjustable. The delay elements can be controlled to maintain uniform phase spacing when ideal sampling is required, or to create non-uniform spacing when early or late sampling is needed for optimized jitter tolerance and timing margins in specific DFE modes.
Data Source
AI summary
Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.