Clock Phase Selection Circuit for Glitch-Free Dynamic PLL Shifting
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Solution Overview
Problem
Existing programmable logic integrated circuits, such as FPGAs, face disruptions when switching between configurations, leading to system functionality loss due to the need to exit user mode for reconfiguration, which is inefficient and can cause glitches in phase-locked loops (PLLs) when dynamically shifting phases.
Innovation Solution
A clock signal generator circuit with a delay circuit, multiplexers, and flip-flops that dynamically adjust phase shifts without causing glitches, allowing PLLs to reconfigure in user mode and maintain phase alignment, using programmable delay cells and barrel shifters to manage phase shifts across multiple phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a new configuration is loaded into the FPGA chip, then the PLL can adapt to changing frequency and noise requirements, but the chip must exit user mode causing system functionality disruption
Solution Approach 1:
The configuration loading process is segmented into separate stages: configuration data is loaded into dedicated storage elements (latches/registers) first, then activated selectively. This allows configuration changes to be prepared without forcing the entire chip out of user mode, enabling partial reconfiguration while maintaining system operation.
Solution Approach 2:
Configuration data is prepared and stored in advance in dedicated storage elements before being activated. The PLL configuration can be pre-loaded while the system continues to operate with existing settings, then switched to new settings without disrupting ongoing operations. This preliminary preparation eliminates the need to exit user mode for reconfiguration.
2Adaptability or versatility
If phase shifting is performed in traditional FPGA circuits, then frequency adaptation is achieved, but glitches occur in the PLL output
Solution Approach 1:
Complementary delay paths are established beforehand to cushion against phase shifting disruptions. When phase shifting is needed, the complementary paths ensure continuous valid signal availability, preventing glitches. The circuit prepares alternative signal paths in advance that can immediately take over without interruption.
Solution Approach 2:
Additional multiplexers and delay elements serve as intermediaries between the phase shifting mechanism and the PLL output. These intermediary components buffer the phase transition, ensuring smooth handover between different phase states without generating glitches in the final output signal.
3Extent of automation
If dynamic phase shifting is implemented, then real-time frequency adjustment is enabled, but circuit complexity increases
Solution Approach 1:
The delay elements and multiplexers are designed to serve multiple functions: they enable phase shifting, provide signal buffering, and support configuration changes. By making these components multi-functional, the circuit achieves dynamic phase shifting capability without proportionally increasing overall complexity, as the same structures perform multiple critical roles.
Data Source
AI summary
A clock signal generator circuit that receives periodic signals has a delay circuit, first and second multiplexers, and flip-flops. The delay circuit delays the periodic signals to generate delayed signals. The first multiplexer selects one of the delayed signals in response to a first select signal to generate an output clock signal. The second multiplexer selects one of the periodic signals in response to a second select signal. The flip-flops generate the first and the second select signals in response to the periodic signal selected by the second multiplexer.