Clock Synthesizer Phase Interpolation for Wideband Low-Noise Output
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Solution Overview
Problem
Existing clock synthesizers have limited frequency coverage and require complex designs and increased costs due to the use of integer dividers and fractional-N dividers, which are costly and occupy significant chip area.
Innovation Solution
A clock synthesizer apparatus incorporating a fractional-N divider controlled by a delta sigma modulator and a phase interpolator, which adjusts the phase of the divided signal based on digital quantization error to reduce noise, allowing for flexible and low-cost frequency generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integer dividers are used in PLL synthesizers, then frequency coverage is limited, but device complexity and cost are reduced
Solution Approach 1:
The divider function is segmented into two independent components: an integer divider that handles the integer portion of the division ratio, and a phase interpolator that handles the fractional portion. This segmentation allows each component to be optimized independently, achieving wide frequency coverage through the phase interpolator while keeping the integer divider simple and low-cost.
Solution Approach 2:
The phase interpolator serves multiple functions: it generates fractional division ratios, provides phase adjustment, and enables wide frequency coverage. By making the synthesizer architecture universal and multi-functional, a single device can cover a broad frequency range without requiring complex fractional-N divider circuits.
2Adaptability or versatility
If fractional-N dividers are used in PLL synthesizers, then frequency coverage is improved, but device complexity and chip area increase
Solution Approach 1:
The fractional-N divider functionality is segmented and replaced by a combination of a simple integer divider and a phase interpolator. The phase interpolator uses a small number of delay elements and multiplexers to achieve fractional division, dramatically reducing the chip area compared to traditional fractional-N divider implementations while maintaining wide frequency coverage.
Solution Approach 2:
Instead of implementing a complex fractional-N divider, the patent uses a phase interpolator that copies and combines multiple versions of the divided signal with different phase delays. This copying approach achieves fractional division ratios using minimal hardware, reducing chip area while maintaining frequency flexibility.
3Adaptability or versatility
If fractional-N dividers are used in PLL synthesizers, then frequency coverage is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting the divider function into an integer divider and phase interpolator, the patent eliminates the need for complex loop filters and VCO control circuits required by traditional fractional-N synthesizers. This simplification reduces manufacturing complexity and cost while achieving wide frequency coverage through the phase interpolator's fractional division capability.
Solution Approach 2:
The patent replaces expensive, complex fractional-N divider circuits with a cheaper alternative using simple delay elements, multiplexers, and an integer divider. Although the phase interpolator requires precise timing, the overall manufacturing cost is reduced by eliminating costly components and simplifying the synthesis architecture.
Data Source
AI summary
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.