Clock Phase Offset Correction for Jitter-Tolerant Signal Processing

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Solution Overview

Problem

As signal data processors shrink and become more complex, clock phase offset issues, particularly dynamic clock offsets induced by temperature and power supply noise, are not adequately addressed by initial calibration, leading to significant jitter problems.

Innovation Solution

A method that continuously measures and adjusts the phase difference between clock signals to maintain a target phase difference, allowing for real-time correction of dynamic clock offsets, in addition to initial static offset calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If initial calibration is performed to correct clock phase offset, then static offset is corrected, but dynamic clock offsets induced by temperature and power supply noise are not addressed

Engineering Contradiction:

Improveclock phase offset correctionVSAvoidjitter tolerance

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the measured phase difference between first and second clock signals is continuously monitored and fed back to adjust the phase offset. This closed-loop system dynamically corrects clock phase offsets caused by temperature and power supply variations, resolving the contradiction between static calibration and dynamic reliability.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent transitions from static initial calibration to dynamic continuous adjustment. The phase offset is no longer fixed after initial calibration but is continuously adapted based on real-time measurements of phase difference, enabling the system to handle dynamic conditions such as temperature changes and power supply noise.

Inventive Principle:

Principle #15Dynamics

2Reliability

If continuous measurement and adjustment of phase difference is implemented, then dynamic clock offsets are corrected, but system complexity increases

Engineering Contradiction:

Improvejitter toleranceVSAvoidsignal processing complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system performs self-correction by automatically measuring its own phase difference and adjusting its own phase offset without external intervention. The signal processing apparatus monitors its own clock signals and autonomously corrects phase offsets, reducing the need for complex external control mechanisms.

Inventive Principle:

Principle #25Self-service

3Reliability

If phase offset is adjusted in real-time, then jitter is reduced, but processing time increases

Engineering Contradiction:

Improvesignal processing accuracyVSAvoidprocessing time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements continuous phase offset correction during signal processing operations. Rather than periodic or discrete adjustments, the phase offset is continuously adapted based on real-time phase difference measurements, ensuring that correction actions are always current without introducing significant delays.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8259888B2Method of processing signal data with corrected clock phase offset

Publication Date: 2012.09.04 RENESAS ELECTRONICS AMERICA INC

AI summary

The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.