Clock Phase Shift Control for Low-Jitter Data Rate Tracking
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Solution Overview
Problem
Synchronous digital systems using spread-spectrum clocking face challenges in accurately tracking changes in data rate due to phase shifts exceeding minimum phase shifts, leading to increased random jitter and phase noise in recovered clock signals.
Innovation Solution
A clock data recovery circuit that adjusts the phases of recovered clock signals by at most a minimum phase shift during each clock cycle, utilizing a sampler circuit, filter circuit, phase shift circuit, and phase interpolator to track data rate changes, thereby reducing quantization error and phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If spread-spectrum clocking is used to reduce electromagnetic interference, then electromagnetic interference is reduced, but tracking accuracy of data rate changes deteriorates due to phase shifts exceeding minimum phase shifts
Solution Approach 1:
The phase shift adjustment is segmented into multiple discrete steps, where each step corresponds to a minimum phase shift. The phase interpolator circuit divides the total phase adjustment range into quantized levels, allowing the system to make fine-grained adjustments rather than large abrupt changes. This segmentation enables accurate tracking of data rate changes while maintaining spread-spectrum clocking benefits.
Solution Approach 2:
The system dynamically changes the phase shift parameter in discrete increments based on detected data rate changes. By adjusting the phase shift parameter in controlled steps rather than continuous or large jumps, the system maintains tracking accuracy while operating under spread-spectrum clocking conditions that reduce electromagnetic interference.
2Adaptability or versatility
If large phase shifts are applied to track data rate changes, then tracking capability is improved, but random jitter and phase noise increase
Solution Approach 1:
Large phase shifts are segmented into multiple minimum phase shift steps. Instead of applying a single large phase shift that would cause signal degradation, the phase interpolator circuit applies multiple smaller incremental adjustments, each staying within the minimum phase shift threshold. This maintains signal quality while achieving the necessary tracking capability.
Solution Approach 2:
The phase adjustment occurs periodically through multiple clock cycles, with each cycle applying a minimum phase shift. This periodic application of small phase shifts achieves the total required phase adjustment over time without causing the random jitter and phase noise that would result from a single large phase shift application.
3Reliability
If phase shifts are limited to minimum values, then random jitter and phase noise are reduced, but tracking speed of data rate changes decreases
Solution Approach 1:
The phase tracking action continues continuously across multiple clock cycles, with each cycle applying a minimum phase shift. This continuous adjustment maintains signal quality by limiting each phase shift to minimum values while achieving fast overall tracking speed through the cumulative effect of multiple sequential adjustments rather than waiting for large infrequent changes.
Data Source
AI summary
A circuit includes a sampler circuit, a filter circuit, a control circuit, and a phase shift circuit. The sampler circuit samples input data in response to a clock signal. The filter circuit is coupled to the sampler circuit. The control circuit is coupled to the filter circuit. The phase shift circuit provides the clock signal to the sampler circuit. The control circuit causes the phase shift circuit to shift a phase of the clock signal by a first phase shift, and by a second phase shift after the phase of the clock signal has shifted by the first phase shift, in response to the filter circuit indicating to shift the phase of the clock signal by more than a predefined phase shift.