Clock-Phase Level Shifter for Low-Voltage Switching Converters
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional level-shifters used in switching converters require large die area and increased components due to high-voltage ratings, and separate source-to-substrate connections, leading to inefficiencies and higher costs.
Innovation Solution
A level-shifter design that transfers logic levels only during specific phases of a clock signal, using a controller to ensure changes occur only when the voltage range is suitable, reducing the need for high-voltage switches and minimizing exposure to excessive voltages, thus allowing low-voltage components to be used safely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level-shifters use high-voltage switches to handle full voltage ranges, then reliability is improved, but device complexity and die area increase
Solution Approach 1:
The patent applies dynamics by making the voltage handling capability of the level-shifter time-varying through clock-phase gating. During the first clock phase, the level-shifter accepts inputs from the high-voltage domain; during the second phase, it outputs to the low-voltage domain. This dynamic switching allows standard low-voltage transistors to safely handle high-voltage signals only when necessary, eliminating the need for dedicated high-voltage transistor pairs and reducing die area.
Solution Approach 2:
The patent implements periodic action by dividing operation into alternating clock phases. The level-shifter operates in a periodic manner: first phase for high-voltage domain signal acceptance, second phase for low-voltage domain signal output. This periodic switching ensures that components are exposed to high voltages only during designated time windows, protecting them from damage while using standard low-voltage components.
2Reliability
If separate source-to-substrate connections are implemented for high-voltage handling, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies universality by using a single substrate connection (second substrate connection) that serves multiple functions across different clock phases. The same physical connection handles both high-voltage signals during the first phase and low-voltage signals during the second phase. This eliminates the need for separate dedicated substrate connections for high-voltage signals, simplifying the fabrication process while maintaining signal integrity through proper timing control.
3Reliability
If high-voltage switches are used to protect components, then component protection is improved, but production cost increases
Solution Approach 1:
The patent applies this principle by using standard low-voltage transistors (which are cheaper and more readily available) instead of expensive high-voltage transistors. The low-voltage transistors are protected from damage by the clock-phase gating mechanism that ensures they are exposed to high-voltage signals only during controlled time windows when they are in a safe state. This approach uses inexpensive components while maintaining reliability through clever timing control.
Data Source
AI summary
Aspects of the present disclosure provide level-shifters and their use with switching converters. A level-shifter receives a binary signal on an input node and generates an output signal also representing the same logic level of the binary signal. The output signal represents logic levels in a first voltage range defined with respect to a first constant reference potential in a sequence of first phases of a clock signal and in a second voltage range defined with respect to a second constant reference potential in a sequence of second phases of the clock signal. The first constant reference potential is lower than the second constant reference potential. A controller block contained in the level-shifter receives the binary signal and transfers a changed logic level of the binary signal only in the first phase, but not in the second phase of the clock signal.