Switching Power Supply Clock Phase Selection for Stable Mode Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Switching power supplies face challenges in transitioning between synchronous and asynchronous operating modes, particularly in maintaining voltage stability during mode changes, as existing solutions can result in significant voltage drops due to improper synchronization of clock signals.
Innovation Solution
The implementation of a switching power supply with a dual-mode operation system, where the clock signal generation circuit synchronizes with either the primary clock signal or its complementary signal based on the rising edge closest to the mode transition, ensuring minimal voltage disruption during mode changes by adjusting the clock signal supply to match the closest rising edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the power supply transitions from asynchronous mode to synchronous mode using a fixed clock signal, then the switching operation can be simplified, but significant voltage drops occur due to improper synchronization
Solution Approach 1:
The clock signal generation circuit dynamically selects between two clock signals (CLK1 and CLK2) based on the operating mode. In synchronous mode, it selects the clock signal whose rising edge is closest to the mode transition instant, thereby adapting the timing to minimize voltage drops while maintaining simplified switching operation.
Solution Approach 2:
The system changes the timing parameter of the clock signal by selecting between two different clock signals with different phase relationships. This parameter change allows the rising edge to be optimally aligned with the mode transition, resolving the contradiction between operational simplicity and voltage stability.
2Device complexity
If the clock signal rising edge is not aligned with mode transition, then circuit design can be simpler, but voltage drops increase during mode changes
Solution Approach 1:
A selection circuit acts as an intermediary between the two clock signals and the switching circuit. This intermediary selectively routes the appropriate clock signal (CLK1 or CLK2) based on the operating mode, achieving optimal voltage stability without significantly increasing overall circuit complexity.
Solution Approach 2:
The clock signal generation is segmented into two distinct clock signals (CLK1 and CLK2) with different timing characteristics. This segmentation allows the system to choose the most appropriate clock signal for each operating mode, minimizing voltage drops while keeping each individual clock signal generation simple.
3Ease of operation
If asynchronous mode is used to reduce switching complexity, then control can be simplified, but voltage stability is compromised during mode transitions
Solution Approach 1:
The system prepares two clock signals in advance with different rising edge timings. When transitioning from asynchronous to synchronous mode, the selection circuit immediately switches to the pre-prepared clock signal whose rising edge is closest to the transition instant, ensuring voltage stability without complicating the control logic.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present description relates to a device comprising a switching power supply configured to have a first mode of operation synchronized by a first clock signal (CLK) generated by a first clock signal generation circuit (48) and a second asynchronous mode of operation, in which the first generation circuit (48) is configured so that the first signal (CLK) becomes equal, during a transition from the second mode of operation to the first mode of operation, to the signal having the closest rising edge among a second clock signal (CLK1) and a third clock signal (/CLK1) complementary to the second clock signal (CLK1).