Clock Phase Alignment Across PVT Variations With Low Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Programmable logic devices, such as FPGAs, face challenges in maintaining stable clock phase alignment due to variations in semiconductor processing corners, power supply voltage, and operating temperature, leading to phase noise and jitter in SERDES applications.
Innovation Solution
A method and apparatus for clock phase alignment that involves adjusting the phase of external and internal clock signals in the physical medium attachment and physical coding clock domains using circuitry loops to maintain alignment and reduce phase noise, employing phase lock loops, programmable delay chains, and alignment systems to compensate for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase lock loops are used for clock phase alignment, then the system can achieve basic clock synchronization, but phase noise and jitter increase due to PVT variations
Solution Approach 1:
The patent implements a feedback mechanism where the aligned clock signal is fed back to continuously adjust and maintain phase alignment. The system monitors phase differences and dynamically adjusts delay elements to compensate for PVT variations, ensuring stable clock synchronization while minimizing phase noise and jitter.
Solution Approach 2:
The patent changes the delay parameter of programmable delay elements based on detected phase differences. By dynamically adjusting the delay value in response to PVT variations, the system maintains accurate clock phase alignment without introducing excessive phase noise or jitter.
2Reliability
If programmable delay chains are used to compensate for PVT variations, then clock phase alignment stability improves, but device complexity increases
Solution Approach 1:
The patent divides the delay compensation function into multiple programmable delay elements arranged in series. Each element can be independently controlled to provide fine-grained phase adjustment, enabling precise clock alignment while distributing the complexity across modular components rather than a single complex element.
Solution Approach 2:
The patent designs the alignment system to perform multiple functions: initial phase alignment, continuous phase tracking, and compensation for PVT variations. By creating a multi-functional system that handles various clock domain scenarios, the patent reduces the need for separate specialized circuits, thereby managing complexity while improving reliability.
3Measurement precision
If multiple alignment loops are implemented for different clock domains, then phase alignment accuracy across domains improves, but system complexity and adjustment requirements increase
Solution Approach 1:
The patent merges the alignment control logic across different clock domains into a unified system. By sharing control mechanisms and delay adjustment logic between multiple clock domains, the system achieves accurate phase alignment across domains while reducing the overall complexity compared to having completely separate alignment loops for each domain.
Data Source
AI summary
A method and apparatus for clock phase alignment are described. An external clock is aligned to an internal clock by adjusting phase of the external clock. The external clock is of a physical medium attachment clock domain, and the internal clock is of a physical coding clock domain. After the aligning of the external clock to the internal clock, the external clock is maintained. The internal clock is aligned to the external clock by adjusting phase of the internal clock.