Clock Phase Interpolator with Independent 90° Quadrant Rotation
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Solution Overview
Problem
Existing 4-quadrant clock phase interpolators lack the ability to perform independent rotation of output clocks in steps of 90°, which is necessary for precise data word alignment and clock alignment in applications like 8b10b encoded data streams.
Innovation Solution
A phase interpolator design incorporating a single level of switches, four transistor loads, and four current sources that allow for independent quadrant rotation by combining the quadrant rotation function with the quadrant selection function, enabling 90° phase shifts without degrading voltage headroom or introducing noise vulnerability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a prior art 4-quadrant phase interpolator design is used, then the basic phase interpolation function is provided, but independent rotation of output clocks in steps of 90° cannot be achieved
Solution Approach 1:
The patent combines the quadrant rotation function with the quadrant selection function into a single level of switches. The switching circuit receives both quadrant select signals and quadrant rotation signals, and merges their control functions to simultaneously achieve both quadrant selection and 90° rotation without adding extra switching levels. This resolves the contradiction by integrating multiple functions into a unified control structure.
Solution Approach 2:
The switching circuit is designed to perform multiple functions: it selects quadrants based on quadrant select signals and simultaneously performs rotation based on quadrant rotation signals. This multi-functional switching circuit eliminates the need for separate circuits for selection and rotation, achieving versatile operation without proportional increase in complexity.
2Adaptability or versatility
If multiple levels of switches are used to achieve quadrant rotation, then rotation function is added, but voltage headroom is degraded and noise vulnerability increases
Solution Approach 1:
The patent merges the quadrant selection switches and quadrant rotation switches into a single level of switching devices. The switching circuit uses one level of switches controlled by both quadrant select signals and quadrant rotation signals, eliminating the need for multiple cascaded switching levels. This reduces the cumulative effect on voltage headroom and minimizes noise vulnerability while maintaining full rotation functionality.
3Ease of operation
If separate circuits for quadrant selection and rotation are used, then independent control is achieved, but device complexity increases
Solution Approach 1:
The patent combines the control functions for quadrant selection and rotation into a single switching circuit. The circuit receives both quadrant select signals and quadrant rotation signals and processes them together to determine the final current source connection. This unified approach maintains independent control capability while avoiding the complexity of separate circuits.
Solution Approach 2:
The switching circuit is designed as a universal control element that handles both quadrant selection and rotation operations. By making the switching circuit multi-functional, the patent achieves independent control of both parameters without requiring separate dedicated circuits, thus maintaining ease of operation without proportional complexity increase.
Data Source
AI summary
The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90°“jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.