Internal Clock Phase Selection Without DDR Data Training
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Solution Overview
Problem
Existing DDR memory devices require time-consuming and power-consuming data training operations to align high speed and main clock signals, and frequency dividers can stop with inverted outputs, necessitating additional training after power up, which affects synchronization and efficiency.
Innovation Solution
An integrated circuit device with a frequency divider and phase controller that generates multiple internal clock signals with the same main clock frequency but different phases, allowing for automatic alignment and synchronization of high speed and main clock signals without the need for data training, using flip-flops and phase selectors to determine the optimal phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If data training operations are used to align high speed and main clock signals, then synchronization accuracy is improved, but time consumption and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-generating multiple internal clock signals with different phases (0°, 90°, 180°, 270°) using frequency dividers and phase shifters before the alignment process. This allows the system to directly select the appropriate phase without performing time-consuming data training operations, thereby achieving fast synchronization with high accuracy.
Solution Approach 2:
The patent changes the phase parameter of internal clock signals by generating multiple signals with different phase offsets (0°, 90°, 180°, 270°) through frequency division and phase shifting. This enables the system to find the optimal phase alignment by selecting from pre-generated options rather than performing iterative training, reducing both time and power consumption while maintaining synchronization accuracy.
2Measurement precision
If data training operations are used to align high speed and main clock signals, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-generating multiple internal clock signals with different phases (0°, 90°, 180°, 270°) using frequency dividers and phase shifters before the alignment process. This allows the system to directly select the appropriate phase without performing power-intensive data training operations, thereby achieving fast synchronization with high accuracy.
Solution Approach 2:
The patent changes the phase parameter of internal clock signals by generating multiple signals with different phase offsets (0°, 90°, 180°, 270°) through frequency division and phase shifting. This enables the system to find the optimal phase alignment by selecting from pre-generated options rather than performing iterative training, reducing both time and power consumption while maintaining synchronization accuracy.
3Use of energy by moving object
If frequency divider stops after power up with data already aligned, then power consumption is reduced, but clock signal alignment may be inverted requiring additional training
Solution Approach 1:
The patent applies self-service by implementing a detection mechanism that automatically monitors the phase alignment status of the frequency divider output after power-up or wake-up from low-power mode. When misalignment is detected, the system automatically triggers a re-alignment operation, eliminating the need for manual intervention or additional training operations, thus ensuring consistent alignment while maintaining low power consumption.
Solution Approach 2:
The patent implements feedback by using a detection circuit to monitor the phase relationship between the frequency divider output and the main clock signal. Based on the detection result, the system provides feedback to control logic that determines whether re-alignment is needed, ensuring reliable and consistent clock synchronization while minimizing unnecessary power-consuming operations.
Data Source
AI summary
An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed.