Clock Signal Phase Selection for Faster High-Speed Synchronization
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Solution Overview
Problem
In modern integrated circuits, synchronizing a local clock signal with an external clock signal is inefficient due to the need for multiple clock signals with different frequencies and issues with jitter and skewing at high speeds, leading to significant lock time delays.
Innovation Solution
Generating three internal clock signals from an external clock signal, each separated by 1tCK or 2tCK, and selecting one based on timing characteristics for synchronization, reducing the length of the delay line and improving locking efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal is used for synchronization, then device complexity is reduced, but lock time increases significantly
Solution Approach 1:
The patent divides the clock signal distribution into multiple parallel paths, each with its own delay line and phase detector. Instead of using one long delay line, the system segments it into multiple shorter delay lines that operate in parallel, reducing the critical path delay and enabling faster lock time while maintaining synchronization capability.
Solution Approach 2:
The patent implements preliminary phase detection and adjustment by generating multiple phase-shifted clock signals in advance through parallel delay lines. The phase detectors pre-evaluate the phase relationships and the multiplexer pre-selects the optimal clock signal before final synchronization is needed, reducing the overall lock time.
2Adaptability or versatility
If multiple clock signals with different frequencies are used, then adaptability to different devices is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal clock distribution system where a single external clock signal can be adapted to drive multiple devices with different frequency requirements. By using parallel delay lines and a multiplexer, the system can generate multiple frequency-divided clock signals from one source, providing universal compatibility without requiring separate clock sources for each device.
Solution Approach 2:
The patent implements dynamic clock signal selection where the multiplexer can switch between different phase-shifted clock signals based on the specific timing requirements of different devices. This dynamic adaptation allows the system to optimize clock distribution for each device individually while maintaining a unified clock source architecture.
3Length of moving object
If a long delay line is used for clock distribution, then synchronization range is improved, but lock time increases
Solution Approach 1:
The patent segments the long delay line into multiple shorter parallel delay lines. Each parallel path has a reduced delay, allowing the system to achieve the same overall synchronization range through parallel processing while reducing the critical path delay and lock time significantly.
Solution Approach 2:
The patent transitions from a single-dimensional sequential delay line to a multi-dimensional parallel architecture. By distributing clock signals through multiple parallel paths simultaneously, the system achieves synchronization across a wide range while reducing the time required, effectively adding a spatial dimension to the clock distribution problem solution.
Data Source
AI summary
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.