Phase-Shifted Clock Selection for Low-Power Signal Sampling
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Solution Overview
Problem
Existing clock signal generation methods for data transmission between sender and receiver with independent internal clocks result in synchronization errors and high power consumption, especially when using high-frequency clock signals.
Innovation Solution
An electric circuit and method that generate multiple clock signals with the same cycle duration but phase-shifted relative to each other, allowing for correlation with a digital signal's characteristic sections to select an optimal clock-sampling signal, reducing the need for high-frequency signals and thus lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency clock signal is used for sampling, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent divides a single high-frequency clock signal into multiple lower-frequency clock signals with different phases (e.g., four clock signals phase-shifted by 90 degrees). This segmentation allows the sampling device to select the most appropriate phase for capturing data transitions, achieving high synchronization accuracy while each individual clock signal operates at a lower frequency, thus reducing power consumption compared to using a single high-frequency clock signal.
Solution Approach 2:
The patent introduces a dynamic selection mechanism that adaptively chooses which clock signal to use based on the actual data signal characteristics. The system dynamically determines the optimal clock signal from the multiple phase-shifted options, allowing the sampling device to adapt to varying data patterns and achieve reliable synchronization without continuously operating at maximum frequency, thereby optimizing power consumption.
2Adaptability or versatility
If multiple clock signals with different phases are generated, then synchronization flexibility is improved, but device complexity increases
Solution Approach 1:
The clock generation device segments a single input clock signal into multiple phase-shifted output signals using a systematic approach (e.g., using delay elements or phase-shift networks). This segmentation provides multiple timing options without requiring multiple independent clock sources, thereby maintaining synchronization flexibility while controlling the growth of device complexity through a structured division approach.
Solution Approach 2:
The patent employs periodic phase-shifting of the clock signal, where multiple clock signals are generated with regular phase intervals (e.g., 90-degree intervals for four signals). This periodic structure provides predictable timing relationships that simplify the selection logic and control mechanisms, reducing the overall system complexity while maintaining high adaptability for different sampling requirements.
Data Source
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AI summary
An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21 - 24, 51 - 54, 61 - 64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51 - 56, 61 - 64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51 - 55, 61 - 64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21 - 24, 51 - 54, 61 - 64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).