Source Synchronous Clock Phase Shift for Cross-Talk Jitter
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Solution Overview
Problem
In high-speed data transmission across multi-chip modules, source synchronous clock systems experience significant noise coupling between clock and data signals, leading to clock edge jitter, which degrades signal fidelity and limits data rates, with existing methods like adding space between signals or using shields being inefficient in reducing noise effectively.
Innovation Solution
The clock signal is intentionally shifted by one-half clock cycle relative to the data signal edges, ensuring noise coupling occurs only during logic states and not during transitions, thereby reducing clock edge jitter and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal is transmitted simultaneously with data signals in a source synchronous system, then high data rates can be achieved, but noise coupling between clock and data signals causes clock edge jitter that degrades signal quality
Solution Approach 1:
The patent applies preliminary action by intentionally shifting the clock signal phase before transmission to occur midway between data transitions. This pre-positioning of the clock edge prevents simultaneous switching with data signals, eliminating the root cause of noise coupling and clock edge jitter while maintaining high data rates.
2Reliability
If space between signal lines is increased to reduce noise coupling, then clock edge jitter is reduced, but the area required for the communication path increases
Solution Approach 1:
The patent changes the temporal parameter (phase timing) of the clock signal rather than modifying the spatial parameter (physical spacing). By shifting the clock phase to occur midway between data transitions, the solution reduces noise coupling through time-domain separation instead of requiring increased physical distance between signal lines.
3Reliability
If shield traces are added between clock and data signals to reduce coupling, then noise is reduced, but device complexity and area increase
Solution Approach 1:
The patent extracts and eliminates the source of the problem by removing the simultaneous switching condition through phase shifting. Instead of adding shielding structures to mitigate the harmful effect, the solution removes the root cause (coincident edges) entirely, thereby eliminating the need for additional shielding complexity.
4Loss of time
If the clock edge is aligned with data transitions for maximum timing efficiency, then setup time requirements are minimized, but cross-talk induced jitter increases
Solution Approach 1:
The patent applies the skipping principle by deliberately positioning the clock edge to skip over the dangerous transition periods of data signals. By rushing through the timing window midway between data transitions, the clock signal avoids the high-risk periods when data edges are changing, thereby minimizing exposure to noise coupling while maintaining efficient timing.
Data Source
AI summary
A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.