Clock Phase Alignment for Deterministic Repetitive Signal Capture
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Solution Overview
Problem
Clocked digital logic circuits face challenges in deterministic signal capture due to variations in signal path and logic design, leading to non-deterministic capture of control/data signals when transitions occur outside the setup/hold window, especially at high clock speeds where timing margins are constrained.
Innovation Solution
A clock module with phase adjustment circuitry aligns the clock-active-edge setup/hold window relative to a repetitive signal, ensuring signal transitions occur within a signal capture window, using clock phase adjustment techniques such as aligning clock inactive edges with signal transitions and averaging phase comparisons to meet predefined setup and hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock speed is increased to improve productivity, then processing speed increases, but timing margins for setup/hold windows decrease leading to non-deterministic signal capture
Solution Approach 1:
The patent implements dynamic clock phase adjustment circuitry that automatically adapts the clock phase to align setup/hold windows with signal transitions. This dynamic adaptation allows the system to maintain deterministic signal capture even at high clock speeds where fixed timing windows would fail, thereby resolving the contradiction between high productivity and reliable signal capture.
2Device complexity
If setup/hold window is fixed relative to clock edge, then clock timing is simple, but signal transitions may fall outside the window causing capture failures
Solution Approach 1:
The patent transforms the fixed setup/hold window into a dynamic window that can be adjusted in phase relative to the clock edge. The phase adjustment circuitry dynamically positions the window to capture signal transitions reliably, maintaining high capture success rates while managing complexity through automated phase alignment mechanisms.
3Reliability
If clock phase is adjusted to align setup/hold window with signal transitions, then deterministic capture is achieved, but additional circuitry and complexity are introduced
Solution Approach 1:
The patent implements a self-adjusting clock phase mechanism where the system automatically detects signal transitions and autonomously adjusts the clock phase to align setup/hold windows with these transitions. This self-service approach minimizes the need for external intervention and complex control logic, achieving deterministic capture while managing complexity through automation.
Data Source
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AI summary
In described examples, clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock (100) with active and inactive clock edges (101, 102) within a clock period (TCLOCK), and signal capture circuitry to capture repetitive signal transitions (20, 21/22) at an active clock edge, based on predefined setup and hold times (tSETUP/tHOLD) which determine a setup/hold window (13). Clock phase adjustment circuitry is configured to adjust clock phase, so that the repetitive signal transitions (20, 21) occur within a signal capture window (14) between setup/hold windows (13). Clock phase adjustment can be based on: aligning the clock inactive edges (102) to the repetitive signal transitions (21); and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to SYSREF timing reference control signal.