Phase Interpolator Current Weighting for Skew-Corrected Clock Phases
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Solution Overview
Problem
Conventional phase interpolator circuits experience phase difference shifts between output clock signals due to skew mismatches, leading to reduced timing margins and hindered high-speed operations.
Innovation Solution
A phase interpolator circuit with a first and second generation circuit generating intermediate currents based on input clock signals, a synthesis circuit for combining these currents, and a correction circuit to adjust current amounts using correction codes to correct phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional phase interpolator circuits are used to generate output clock signals, then the circuit can operate at high speed, but phase difference shifts occur between output clock signals due to skew mismatches, reducing timing margins
Solution Approach 1:
The patent applies preliminary action by measuring the phase difference between input clock signals in advance and storing the measurement result in a register. Before generating output clock signals, the system reads the stored phase difference value and uses it to pre-adjust the weighting coefficients in the synthesis circuit, thereby compensating for skew mismatches before they affect the output timing margin.
Solution Approach 2:
The patent implements feedback by continuously measuring the phase difference between input clock signals using a phase difference measurement circuit, storing the measured value, and using this information to adjust the synthesis weights in subsequent operations. This closed-loop feedback mechanism ensures that phase difference shifts are compensated, maintaining reliable timing margins while preserving high-speed operation.
2Reliability
If phase difference measurement and correction circuits are added to correct skew mismatches, then timing margins are maintained, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into unified circuit blocks to reduce complexity. The phase difference measurement circuit is integrated with the synthesis circuit, and the correction mechanism is combined with the existing phase interpolator structure. By merging these functions rather than adding separate independent circuits, the patent maintains timing margins while minimizing the increase in device complexity.
Data Source
AI summary
A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.