Clock Phase Switching Circuit for Wireless Spur Reduction
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Solution Overview
Problem
In wireless receiving devices, harmonics of the clock signal generated by digital circuits can introduce spurious components into analog circuits, degrading receiving sensitivity and requiring effective countermeasures to reduce these unwanted radiation components.
Innovation Solution
A clock generation circuit that modulates the edge timing of the clock signal by advancing or delaying it by a fixed amount corresponding to a desired frequency band, using multiple delay lines and a select circuit to periodically switch between different clock signal phases, effectively canceling spurious components in the desired frequency band.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is generated for digital circuit operation, then digital circuit functionality is enabled, but spurious components are introduced into analog circuit causing receiving sensitivity degradation
Solution Approach 1:
The patent applies periodic action by modulating the clock signal edge timing periodically between advanced and delayed phases. The edge timing modulation unit alternates between advancing and delaying the clock signal edges at regular intervals, which spreads the spurious components across frequency bands and reduces their concentration in the desired frequency band, thereby improving receiving sensitivity while maintaining digital circuit operation
Solution Approach 2:
The patent changes the timing parameter of the clock signal by advancing or delaying the edge timing by a fixed amount corresponding to a desired frequency band. This parameter change modulates the clock signal phase periodically, which transforms the spectral distribution of spurious components and reduces their impact on receiving sensitivity
2Reliability
If clock signal edge timing is modulated to reduce spurious components, then receiving sensitivity is improved, but device complexity increases due to additional delay lines and select circuits
Solution Approach 1:
The patent segments the clock signal path into multiple parallel delay lines (first delay line, second delay line, third delay line) with different delay amounts. A select circuit then chooses between these segmented paths based on the desired modulation state. This segmentation approach enables edge timing modulation while maintaining a relatively simple circuit structure by using discrete, independent delay elements
Data Source
AI summary
A clock circuit includes a selector circuit connected to an output terminal, first, second, and third paths connected in parallel between an input terminal for receiving an input clock signal and the selector circuit, a first clock signal output from the first path being delayed with respect to a second clock signal output from the second path by a predetermined length of time, and the second clock signal being delayed with respect to a third clock signal output from the third path by the predetermined length of time, and a control circuit configured to control the selector circuit to switch among at least two of the first, second, and third clock signals.