Time-to-Digital Converter Stop Control for Injection-Locking Noise
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Solution Overview
Problem
Existing phase frequency detectors (PFDs) face challenges in accurately determining phase differences between clock signals due to injection locking effects, where a second oscillator can capture a first oscillator, leading to phase noise and reduced measurement resolution.
Innovation Solution
The proposed electronic circuit includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry, which uses a pseudo-random binary sequence generator to randomize the stop signal selection, thereby improving phase difference measurement accuracy and reducing noise by 'dithering' the timing output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a timer circuit is used to measure phase difference between clock signals, then phase difference measurement capability is achieved, but measurement precision deteriorates due to injection locking effects causing phase noise
Solution Approach 1:
The patent applies dynamics by making the stop signal selection variable and time-varying through random selection from multiple delay stages, rather than using a fixed stop signal. This dynamic approach randomizes the timing of stop signals to different delay stages, which spreads out the phase noise caused by injection locking effects across different measurement instances, thereby improving overall measurement precision without sacrificing reliability
Solution Approach 2:
The patent changes the parameter of stop signal delay by selecting from multiple delay stages with different delay amounts. By varying the delay parameter randomly across measurement cycles, the system transforms the static measurement process into a dynamic one that averages out injection locking-induced phase noise, resolving the contradiction between measurement precision and reliability
2Measurement precision
If multiple delay stages are used to provide stop signal options, then measurement resolution is improved, but device complexity increases
Solution Approach 1:
The patent segments the timing measurement function into multiple parallel delay stages, each providing a specific delay amount. This segmentation allows the system to achieve fine measurement resolution by selecting from discrete delay stages, while the modular segmented structure makes the increased complexity manageable and organized rather than monolithic
3Reliability
If random selection of stop signal delay stages is implemented, then noise spurs are reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces a random number generator as an intermediary component that selects which delay stage output serves as the stop signal. This intermediary random selection mechanism spreads narrowband noise spurs caused by injection locking across a wider frequency spectrum, converting concentrated noise into distributed noise that can be more easily filtered, thereby improving reliability while adding only moderate circuit complexity
Data Source
AI summary
In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.