Clock Signal Phase Adjustment for Multi-Unit Synchronization
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Solution Overview
Problem
Existing methods for synchronizing the states of multiple sequential processing units, especially at high frequencies, face challenges when a common reset signal is not practical due to distance-related timing errors and increased hardware complexity, particularly in communication systems and measurement instruments.
Innovation Solution
The approach involves generating multiple clock signals from a common clock signal, adjusting the phase of at least one clock signal, and using feedback control to synchronize the states of processing units by determining synchronization errors and adjusting the clock rate or phase to match the states of other units, allowing for continuous phase rotation without discontinuity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common reset signal is distributed to synchronize multiple sequential processing units, then state synchronization is achieved, but timing errors increase and hardware complexity increases due to distance-related path mismatches
Solution Approach 1:
The patent introduces a mediator mechanism (the second sequential processing unit acting as a reference) that indirectly synchronizes the first and third processing units. Instead of directly comparing both units to a common reset signal, the system uses the second unit as an intermediary reference point, allowing synchronization without direct long-path signal distribution.
Solution Approach 2:
The synchronization problem is segmented into multiple local comparisons rather than one global comparison. The first processing unit is synchronized with the second, and the third is synchronized with the second, creating separate synchronization segments that avoid the timing errors of a single long-distance common reset signal path.
2Reliability
If a common reset signal is distributed to synchronize multiple sequential processing units, then state synchronization is achieved, but device complexity increases
Solution Approach 1:
The second sequential processing unit serves multiple functions: it operates as a normal processing unit performing its designated function, and simultaneously serves as a reference unit for synchronizing both the first and third processing units. This multi-functionality eliminates the need for separate dedicated reference circuitry.
Solution Approach 2:
The system uses its own internal resources (the second processing unit's clock signal and state) to provide synchronization services to other units, rather than requiring external synchronization infrastructure. The second unit essentially serves itself and others simultaneously.
3Reliability
If clock signals are phase-shifted to synchronize processing units at high frequencies, then state synchronization is achieved, but timing precision requirements increase
Solution Approach 1:
The patent employs feedback mechanisms where the state of the second processing unit (serving as reference) is continuously monitored and used to adjust the clock signals to the first and third units. This feedback loop automatically compensates for phase drift and maintains synchronization without requiring manual precision adjustment.
Solution Approach 2:
The system transitions from static phase settings to dynamic phase adjustment. The clock signal phases are continuously adapted based on the actual operating conditions and drift characteristics of the processing units, allowing the system to maintain synchronization despite variations in temperature, voltage, and frequency.
Data Source
AI summary
The invention provides a device for providing a plurality of clock signals from a common clock signal. The device comprises an input (101) for receiving the common clock signal, a first clock signal path (109) for providing a first output clock signal on the basis of the common clock signal and a second clock signal path (111) for providing a second output clock signal. The second clock signal path (111) comprises a clock processing means (113) for changing a phase of the common clock signal to provide the second clock signal.