Clock Phase Synchronization via Sampled Password Sequences
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Solution Overview
Problem
The challenge of achieving high-precision clock synchronization in communication devices is hindered by clock signal delays, hardware aging, temperature drift, and device inconsistencies, which lead to increased time output deviations and difficulty in meeting precise synchronization requirements.
Innovation Solution
A method involving a master clock apparatus that samples an initial password sequence from a first key clock signal, sends it to a slave clock apparatus, and synchronizes the phase of a second key clock signal using a sampled password sequence, allowing the slave clock apparatus to adjust its phase to match the master's phase, thereby achieving synchronization without manual compensation or loopback lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional hardware measurement and manual compensation methods are used for clock synchronization, then device complexity is reduced, but synchronization precision deteriorates due to unavoidable clock signal delays, aging, temperature drift, and device inconsistencies
Solution Approach 1:
The patent replaces traditional hardware-based manual measurement and compensation methods with an automated software-based sampling and processing system. The master clock apparatus automatically samples the password sequence according to the first key clock signal, processes the sampled data, and transmits control information to the slave clock apparatus for automatic phase adjustment, eliminating manual intervention and achieving high-precision synchronization.
Solution Approach 2:
The patent implements a feedback mechanism where the master clock apparatus transmits control information based on the sampled password sequence to the slave clock apparatus. The slave clock apparatus adjusts its phase according to this feedback information, creating a closed-loop system that continuously monitors and corrects synchronization deviations, thereby achieving precise clock synchronization.
2Measurement precision
If automated sampling and processing methods are implemented, then synchronization precision is improved, but device complexity increases due to additional sampling modules, processing units, and communication interfaces
Solution Approach 1:
The patent applies multi-functionality by integrating the sampling module, processing unit, and communication interface into existing clock synchronization hardware. The sampling module utilizes the existing key clock signal generation circuitry, the processing unit leverages available processor resources, and the communication interface uses existing data transmission channels, thereby achieving automated synchronization without proportionally increasing device complexity.
3Productivity
If manual compensation methods are used, then ease of operation is maintained, but productivity decreases due to time-consuming manual measurement and adjustment processes
Solution Approach 1:
The patent implements self-service by enabling the clock synchronization system to automatically perform measurement, processing, and adjustment operations without manual intervention. The master clock apparatus autonomously samples the password sequence, processes the data to determine phase differences, and transmits control information to the slave clock apparatus, which automatically adjusts its phase, thereby significantly improving synchronization efficiency while maintaining ease of operation through automated functionality.
Data Source
AI summary
The present application discloses a clock synchronization method, apparatus and system, an electronic device and a readable medium. The method includes: sampling an initial password sequence according to a first key clock signal to obtain a sampled password sequence; and sending the first key clock signal and the sampled password sequence to a slave clock apparatus to synchronize a phase of a second key clock signal with a phase of the first key clock signal, with the second key clock signal determined by the slave clock apparatus according to the first key clock signal and the sampled password sequence.