Clock Phase Prediction for Accurate Multi-Frequency Timestamping
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Solution Overview
Problem
Existing phase predictors lack the necessary accuracy for modern equipment environments and are limited in supporting different clock frequencies, which affects synchronization in digital phase locked loops, Precision Time Protocol systems, and 5G telecom networks.
Innovation Solution
A system and method that predicts the phase relationship between two clock signals by determining an event clock cycle prediction, emulating a predicted event clock, and aligning it with the system clock, allowing for improved timestamp accuracy across different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing phase predictors are used to predict phase relationship between clocks, then basic phase detection is achieved, but accuracy is insufficient for modern equipment environments requiring below 5 ns total time error
Solution Approach 1:
The phase prediction process is segmented into multiple independent components: event clock cycle prediction module, phase difference calculation module, and timestamp adjustment module. Each segment handles a specific aspect of the prediction, allowing for higher precision through specialized processing while maintaining system reliability through modular error handling.
Solution Approach 2:
The system performs preliminary event clock cycle prediction before actual timestamp generation. By predicting the phase relationship in advance and using this prediction to adjust timestamps proactively, the system achieves below 5 ns accuracy without requiring complex real-time measurement systems.
2Adaptability or versatility
If existing phase predictors are used, then implementation is achieved, but they support only limited specific clock rates and cannot adapt to different clock frequencies
Solution Approach 1:
The phase predictor is designed with universal functionality to handle multiple clock frequencies and domains. The event clock cycle prediction mechanism adapts to different clock rates by dynamically calculating phase relationships based on actual clock periods, allowing the same hardware to serve multiple synchronization scenarios without requiring frequency-specific configurations.
Solution Approach 2:
The system changes its operational parameters dynamically based on the input clock frequencies. By adjusting the prediction interval, sampling rate, and calculation precision according to the specific clock domains involved, the predictor maintains accuracy across different frequency scenarios while avoiding the complexity of multiple fixed-configuration units.
3Measurement precision
If higher accuracy phase prediction is implemented, then timestamp precision improves, but system complexity and implementation cost increase
Solution Approach 1:
The patent introduces an intermediary event clock cycle prediction mechanism that mediates between the system clock domain and event clock domain. This intermediary layer calculates phase relationships using simplified mathematics based on clock period ratios, achieving high timestamp accuracy without requiring complex direct measurement circuits between clock domains.
Solution Approach 2:
The system replaces complex mechanical or electronic phase measurement hardware with software-based mathematical calculations. By using algorithms to compute phase differences from clock period ratios and counters, the patent achieves picosecond-level timestamp precision while maintaining implementation simplicity and reducing hardware complexity.
Data Source
AI summary
A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.