Clock Phase Detection Circuit for Stable High-Speed Training
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Solution Overview
Problem
High-speed semiconductor devices face instability in clock alignment training due to phase differences between system and data clocks, leading to unreliable phase detection and prolonged training times, especially at high frequencies.
Innovation Solution
A circuit that simultaneously detects phases of system and data clocks by generating multiple multi-system clocks with individual phase differences and a data dividing clock with the same frequency, using phase comparing units and logic level changing units to minimize noise influence on the training information signal, allowing for stable clock alignment training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock alignment training is performed in high-speed semiconductor devices, then synchronization between system clock and data clock is achieved, but phase differences cause instability and unreliable detection
Solution Approach 1:
The patent divides the phase detection process into multiple stages by generating multiple divided clocks from the system clock at different frequencies. This segmentation allows the phase detector to compare the data clock against multiple reference phases, thereby reducing the impact of phase differences and improving detection reliability in high-speed operations.
Solution Approach 2:
The patent introduces a clock dividing unit as an intermediary component that generates multiple divided clocks from the system clock. These divided clocks serve as intermediate references that bridge the phase difference between the system clock and data clock, enabling accurate phase detection without direct comparison of the original high-frequency signals.
2Productivity
If data clock frequency is doubled to input/output four data per system clock period, then data throughput increases, but training time is prolonged
Solution Approach 1:
The patent performs preliminary clock alignment training by pre-generating multiple divided clocks at different frequencies before the actual data transmission begins. This preliminary preparation allows the phase detector to quickly determine the correct phase relationship without requiring extended training time during high-speed operation.
Solution Approach 2:
The patent generates more divided clocks than strictly necessary (excessive action) to ensure sufficient phase reference points for accurate detection. By providing multiple over-sampled reference phases, the system can rapidly identify the optimal alignment without requiring proportional training time extension.
3Productivity
If phase difference exists between system clock and data clock, then data transmission can proceed, but timing alignment is incorrect causing operational errors
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase relationship between the data clock and the divided system clocks, then transmits phase difference information back to the external controller. This feedback loop enables dynamic adjustment of the data clock phase to maintain correct timing alignment during high-speed data transmission.
Solution Approach 2:
The patent replaces direct mechanical timing alignment with an electronic phase detection and adjustment system. Instead of relying on fixed hardware synchronization, the system uses electronic signal processing to detect phase differences and transmit correction information, enabling more flexible and reliable timing alignment in high-speed operations.
Data Source
AI summary
A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal.