Interface Clock Phase Tuning for Serial Interface Latency
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Solution Overview
Problem
Processor-based emulation systems face latency issues and read errors due to mismatches in clock frequencies and phases between processing core clocks and interface clocks, particularly in serial data transmission and reception.
Innovation Solution
A training processor tunes the phases of interface clocks during the system's bring-up phase to align them with the processing core clock, accounting for factors like hold and setup times, clock jitter, and skew, ensuring stable data transfer and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processing core clock and interface clock have different frequencies and phases, then the system can operate with higher productivity through parallel processing, but read errors and higher latency occur due to clock mismatch
Solution Approach 1:
The patent applies preliminary action by performing phase tuning of interface clocks relative to the processing core clock during the power-up (bring-up) phase before normal operation begins. The training processor executes training software that adjusts clock phases in advance, ensuring that when data transfer operations commence, the clocks are already synchronized to prevent read errors and minimize latency, thus maintaining both high productivity and reliability.
2Reliability
If data is stored in the buffer for longer duration to accommodate clock mismatch, then read errors are avoided, but latency increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the phase parameter of the interface clock relative to the processing core clock. During the bring-up phase, the training software modifies the clock phase parameter to achieve optimal alignment, allowing data to be transferred with minimal buffering time while maintaining data integrity. This eliminates the need for extended buffer storage periods that would increase latency.
3Reliability
If clock phases are tuned during bring-up phase, then latency is minimized and read errors are avoided, but the system requires additional training processing time
Solution Approach 1:
The patent performs clock phase tuning as a preliminary action during the bring-up phase, which is an acceptable overhead time before the system enters normal high-performance operation. The training processor executes phase adjustment algorithms in advance, and once tuned, the system maintains stable data transfer with minimal latency during productive operation. This preliminary investment in phase calibration ensures long-term reliability without impacting ongoing productivity.
Data Source
AI summary
Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.