Clock Generation Circuit Timing to Prevent Phase-Update Jitter
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Solution Overview
Problem
Existing clock generation circuits in semiconductor devices face challenges in accurately compensating for phase differences between internal clock signals and system clock signals, leading to potential random jitter and malfunctions in internal circuits.
Innovation Solution
The proposed clock generation circuit incorporates a delay-locked circuit and a duty correction circuit, which generate multiple phase clock signals by delaying an input clock signal and adjust the delay times based on phase comparisons to prevent simultaneous updates, thereby maintaining proper phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the delay time of the input clock signal and the delay time of the delay clock signal are updated simultaneously, then the phase compensation can be performed faster, but random jitter and malfunctions occur in internal circuits
Solution Approach 1:
The patent implements periodic action by controlling the update timing of delay times. The delay time of the delay clock signal is updated only in specific periods when the delay time of the input clock signal is not being updated. This periodic, non-simultaneous update approach prevents random jitter and malfunctions while still achieving effective phase compensation over time.
2Measurement precision
If the delay time of the delay clock signal is updated frequently, then the phase accuracy is improved, but random jitter increases in the clock signals
Solution Approach 1:
The patent applies periodic action by updating the delay time of the delay clock signal only in specific periods rather than continuously or frequently. This controlled periodic updating maintains phase accuracy while avoiding the random jitter that would result from frequent updates.
Solution Approach 2:
The patent implements preliminary action by determining the update timing of the delay clock signal based on the update timing of the input clock signal. The system proactively schedules updates to avoid simultaneous updates, thereby preventing random jitter before it occurs.
3Device complexity
If a single delay control mechanism is used, then the device complexity is reduced, but the ability to prevent simultaneous updates and maintain phase differences is insufficient
Solution Approach 1:
The patent implements feedback by having the delay control circuit control the update timing of the delay clock signal based on the update timing of the input clock signal. This feedback mechanism ensures that updates do not occur simultaneously, maintaining proper phase differences between clock signals while using a relatively simple control structure.
Data Source
AI summary
A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.