Clock Phase Shifting for Voltage-Droop Timing Margin Control
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Solution Overview
Problem
Conventional computing architectures face inefficiencies in timing latency, performance, and power dissipation due to inadequate voltage margin management during voltage transients, leading to timing errors and increased power consumption.
Innovation Solution
A flexible clocking architecture that includes a droop detector, phase shifter, and digital locked loop to dynamically adjust the CPU/GPU clock frequency in response to voltage droops, reducing power dissipation by momentarily lowering digital circuit speed without degrading user experience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional computing circuitry operates at higher voltage to maintain timing margins during voltage transients, then timing reliability is improved, but power dissipation increases
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time voltage conditions. A voltage monitor detects voltage droops and triggers clock frequency reduction through a phase-locked loop, allowing the system to adapt timing margins to actual voltage conditions rather than maintaining fixed high-voltage operation, thereby reducing power dissipation while maintaining timing reliability when needed
Solution Approach 2:
The system changes the clock frequency parameter in response to voltage transient conditions. When voltage droop is detected, the phase-locked loop adjusts the clock frequency to extend timing margins, effectively changing the timing parameter to compensate for voltage variations without requiring increased supply voltage
2Loss of energy
If clock frequency is reduced to lower power dissipation during voltage transients, then power efficiency is improved, but timing performance degrades
Solution Approach 1:
The system employs a voltage monitor that continuously monitors supply voltage and provides feedback to the phase-locked loop. When voltage droop is detected, the feedback mechanism triggers clock frequency adjustment to extend timing margins, ensuring timing performance is maintained during voltage transients while avoiding unnecessary frequency reduction during stable voltage conditions, thus optimizing power efficiency
Solution Approach 2:
The phase-locked loop is configured to proactively adjust clock frequency in anticipation of timing violations during voltage droop events. By detecting voltage transients early and preemptively extending timing margins through frequency adjustment, the system prevents timing errors before they occur while minimizing the duration and magnitude of frequency reduction to maintain overall productivity
3Reliability
If voltage margin is increased to prevent timing errors during transients, then timing reliability is improved, but device complexity increases
Solution Approach 1:
The system introduces a voltage monitor as an intermediary component that detects voltage droop conditions and triggers the phase-locked loop for clock frequency adjustment. This intermediary mechanism automates the voltage margin management process, replacing complex manual voltage scaling controls with a streamlined detection-response system that improves timing reliability during transients while keeping the control architecture relatively simple
Data Source
AI summary
Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.