Programmable Clock Phase Circuit Without DLL Locking Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation circuits that use delay-locked loops (DLLs) do not scale well to smaller critical dimensions, leading to inefficiencies and reduced performance in applications such as analog-to-digital converters (ADCs).
Innovation Solution
A generating circuit that provides an edge clock with a target phase within a clock period of an input clock, utilizing a gated ring oscillator and a control circuit to determine the reference count and generate the edge clock without relying on a DLL. This circuit is programmable and can adjust the fundamental frequency and duty cycle of the edge clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop (DLL) is used to generate multiple clock edges within a clock period, then the clock generation function is achieved, but the circuit does not scale well to smaller critical dimensions
Solution Approach 1:
The patent replaces the analog DLL mechanism with a digital counter-based system. The counter increments on each input clock edge and generates output edges when the count reaches predetermined values, eliminating the need for analog delay elements that do not scale to smaller dimensions.
Solution Approach 2:
The patent changes the operating parameters by using digital counting values instead of analog delay times. The counter can be programmed with different threshold values to generate multiple clock edges (e.g., 8, 16, or 32 edges) within a clock period, providing flexibility without relying on analog circuit scaling.
2Ease of operation
If complicated analog circuits are used to generate edges within the period of the input clock, then the clock edge generation is achieved, but the circuits do not scale well as process nodes are reduced
Solution Approach 1:
The patent substitutes complex analog timing circuits with a simple digital counter and comparator logic. The counter increments on each clock edge and uses digital comparators to detect when the count reaches predetermined thresholds, generating output edges without requiring complex analog delay elements.
Solution Approach 2:
The patent segments the clock period into discrete intervals using digital counting. Each output clock edge corresponds to a specific count value, allowing precise control over the timing and number of output edges through digital programming rather than analog circuit design.
3Ease of operation
If a DLL is used to generate multiple clock edges, then the clock phase generation is achieved, but the response time is reduced
Solution Approach 1:
The patent replaces the feedback-based DLL mechanism with a feedforward digital counter system. The counter immediately generates output edges based on the input clock edges without requiring loop locking, significantly improving the response time to changes in input clock frequency or phase.
Data Source
AI summary
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.