Clock Polarity Control Circuit for Phase-Correlated Divider Outputs
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Solution Overview
Problem
In wireless communication systems, particularly in advanced antenna systems and MIMO systems, the polarity of clock signals generated by frequency dividers is often unknown, leading to potential phase correlation issues when multiple frequency dividers are used, which can cause operational problems.
Innovation Solution
A clock signal polarity controlling circuit is introduced, utilizing a combination of latches and an XOR circuit to compare the output signal from a clock signal generator with a reference clock signal, allowing for the generation of a clock signal with controlled polarity, either matching or opposing the reference signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a latch based frequency divider is used to generate IQ clock signals, then the frequency division function is achieved, but the output signal polarity becomes unknown and cannot be controlled
Solution Approach 1:
The patent introduces a feedback mechanism where the output of the frequency divider is fed back through latches and XOR circuits to detect and correct the polarity. The system continuously monitors the output polarity and uses feedback signals to control the polarity correction, ensuring the output polarity matches the desired reference polarity.
Solution Approach 2:
The patent uses intermediate latches and XOR circuits as mediators between the frequency divider output and the final output. These intermediate components detect the actual polarity and generate correction signals without altering the core frequency division function, allowing polarity control while maintaining productivity.
2Adaptability or versatility
If multiple frequency dividers are used in the system, then the frequency conversion requirements are met, but phase correlation issues arise due to unknown polarities
Solution Approach 1:
The patent creates a universal polarity control mechanism that can be applied to multiple frequency dividers throughout the system. The same latch-XOR feedback structure can be replicated across different frequency divider stages, providing consistent polarity control and ensuring phase correlation across all converted frequencies.
Solution Approach 2:
The patent replaces physical/mechanical phase alignment methods with electronic feedback control. Instead of relying on fixed mechanical relationships between multiple frequency dividers, the system uses electronic detection and correction through latches and XOR circuits to achieve precise phase correlation.
3Device complexity
If the output polarity is set at start-up, then the circuit operation is simplified, but the polarity becomes fixed and cannot be adjusted later
Solution Approach 1:
The patent transforms the static polarity setting into a dynamic, adjustable parameter. The feedback mechanism allows the polarity to be continuously monitored and adjusted based on the desired output, making the system adaptable to different operating conditions while maintaining relatively simple circuit operation through reusable latch-XOR modules.
Data Source
AI summary
A clock signal polarity controlling circuit comprises a first latch comprising a clock input, a data input and an output. The data input is coupled to an output of a clock signal generator, the clock input is coupled to a reference clock signal. The clock signal polarity controlling circuit further comprises a second latch comprising a clock input, a data input and an output. The data input is coupled to the output of the first latch, the clock input is coupled to the reference clock signal. The circuit further comprises an XOR circuit comprising a first and second inputs and an output. The first and second inputs are coupled to the output of the second latch and the output of the clock signal generator respectively, and a clock signal having a polarity controlled by the reference clock signal is generated at the output of the XOR circuit.