Clock Transmission Over Packet-Switched Networks

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Solution Overview

Problem

Conventional clock transmission methods over Packet-Switched Networks (PSNs) face challenges due to Packet Delay Variation (PDV) and packet loss, which affect the jitter and wander quality of restored clocks, especially when transmitting Time Division Multiplex (TDM) services.

Innovation Solution

A method and system where the sender generates clock information relative to a system clock and sends it in data packets over PSNs, allowing the receiver to restore the clock without being affected by PDV and packet loss, using a clock information generation module, packet assembly module, disassembly module, clock information analyzing and filtering module, and clock restoring module to adapt and smooth the clock signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional circuit simulation method is used to restore the clock of the TDM service over PSN, then the clock can be restored, but the jitter and wander quality of the restored clock deteriorates due to packet delay variation and packet loss

Engineering Contradiction:
Improveclock restoration reliabilityVSAvoidjitter and wander quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent extracts clock information from data packets and creates a copy of the original clock signal at the receiver. Instead of relying on circuit simulation that is sensitive to network impairments, the system copies the actual clock characteristics embedded in the transmitted data packets, thereby restoring the clock with high precision despite packet delay variation and loss.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces clock information as an intermediary element that carries timing characteristics through the packet-switched network. This intermediary allows the clock signal to be transmitted indirectly within data packets, protecting it from the harmful effects of network impairments while maintaining synchronization between sender and receiver.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a clock switched matrix is established to switch the clock together with the service in OTN switched system, then the service switching is enabled, but the device complexity and cost increase significantly due to high frequency requirements

Engineering Contradiction:
Improveservice switching capabilityVSAvoidclock switched matrix complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges clock switching with data packet switching by embedding clock information within the data packets themselves. Instead of requiring a separate clock switched matrix operating at high frequencies, the system combines clock transmission with existing data packet routes, thereby enabling service switching without the complexity and cost of dedicated high-frequency clock switching infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system copies clock information into data packets that are already being switched through the OTN system. This approach allows the existing packet switching infrastructure to handle both data and clock synchronization functions, eliminating the need for separate high-frequency clock switching hardware and reducing overall system complexity.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables reliable clock transmission between sender and receiver, reducing the impact of network impairments and facilitating clock switching in high-frequency Optical Transport Network (OTN) systems, while reducing costs associated with clock switched matrices.

Implementation Method 1

The local clock is generated through filtering by a phase-locked loop (PLL) according to the state of the FIFO

Methodology Applied
Scientific EffectPhase-locked loop:

Data Source

PatentUS7792157B2Method, system and device for clock transmission between sender and receiver
Publication Date: 2010.09.07 HUAWEI TECH CO LTD
  • US7792157B2 patent drawing
  • US7792157B2 patent drawing
  • US7792157B2 patent drawing

AI summary

Embodiments of the present invention provide a method, system and device for clock transmission between a sender and a receiver. The sender generates clock information of a clock to be sent relative to a system clock and sends a data packet containing the clock information to the receiver over a Packet-Switched Network (PSN). The receiver obtains the clock information in the data packet received and obtains the clock sent by the sender according to the clock information and the system clock. According to the embodiments of the present invention, after the clock of the sender is transmitted over the PSN, the receiver may obtain the clock of the sender without being affected by such damage as a network delay jitter and a packet loss.