Clock Pulse Circuit for Overlap-Free DDR SDRAM Timing
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Solution Overview
Problem
Conventional clock pulse generating circuits in DDR SDRAMs face issues with signal overlap and deterioration of characteristics like tAC and tDQSCK, especially at high frequencies, due to skew between rising and falling clock signals, leading to unstable clock pulse supply and synchronization problems.
Innovation Solution
A clock pulse generating circuit is designed with a pulse generator to vary pulse widths of rising and falling clock signals, a clock regulator to prevent overlap and duty drop, and a pre-driver to output data driving signals, utilizing delay and logic units to regulate and synchronize the signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pulse generator operates at high frequencies, then the productivity of the memory device is improved, but the clock pulse signals may overlap and the characteristics tAC and tDQSCK deteriorate
Solution Approach 1:
The patent applies preliminary action by generating the inverted clock signal FCLKDLL in advance through the DLL circuit, and using it to control the pulse generation timing. The pulse generator uses this pre-generated inverted signal to determine when to generate RCLKDO and FCLKDO pulses, ensuring that pulses are generated only when the other signal is low, thus preventing overlap before it can occur at high frequencies
Solution Approach 2:
The patent introduces an intermediary control mechanism where the inverted clock signal FCLKDLL acts as a mediator to control the pulse generation of both RCLKDO and FCLKDO. The pulse generator uses this intermediary signal to coordinate the timing of pulse outputs, ensuring that pulses are generated during the low period of the inverted signal, thereby preventing overlap while maintaining high-frequency operation
2Manufacturing precision
If the pulse width is increased to ensure proper signal levels, then the signal integrity is improved, but the clock signals may overlap at high frequencies
Solution Approach 1:
The patent applies dynamics by making the pulse width adaptive rather than fixed. The pulse generator dynamically adjusts the pulse width of RCLKDO and FCLKDO based on the timing of the inverted clock signal FCLKDLL. The pulses are generated for a duration determined by the low period of FCLKDLL, allowing the pulse width to automatically adapt to different operating frequencies and prevent overlap while maintaining sufficient signal levels
Solution Approach 2:
The patent changes the parameter of pulse width from a fixed value to a variable parameter controlled by the inverted clock signal. The pulse generator modifies the pulse width parameter dynamically based on the timing characteristics of FCLKDLL, ensuring that pulses maintain adequate width for signal integrity while adapting to high-frequency operation conditions to prevent overlap
3Device complexity
If skew between rising and falling clock signals is allowed, then the device complexity is reduced, but the characteristics tAC and tDQSCK deteriorate
Solution Approach 1:
The patent applies equipotentiality by ensuring that both RCLKDO and FCLKDO pulses are generated under the same timing reference (the inverted clock signal FCLKDLL). This creates symmetric timing conditions for both rising and falling clock outputs, eliminating skew between them while maintaining circuit simplicity through the unified control mechanism of the pulse generator
Data Source
AI summary
A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator.