Clock Pulse Deletion for SoC Frequency Adaptation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semi-conductor devices with multiple processing elements on a system on chip (SoC) face challenges in data transfer due to differing clock frequencies, leading to increased complexity and latency when non-integer clock ratios are required, and dynamic variation of clock speed is difficult to achieve for optimal processing.
Innovation Solution
A system that fine-tunes the effective clock rate of each module by using clock gating cells controlled by a clock deletion control unit, allowing for arbitrary reduction of clock pulses to achieve desired frequencies, and ensures safe data transfer between modules through clock pulse forcing or two-way handshake protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If arbitrary clock ratios are used between processing elements, then processing flexibility is improved, but data transfer complexity and latency increase
Solution Approach 1:
A clock deletion control unit acts as an intermediary between the master clock source and individual processing elements. This unit selectively deletes clock pulses to achieve arbitrary clock ratios without requiring complex synchronization logic or FIFO buffers at data transfer interfaces, thereby maintaining simple data transfer paths while enabling flexible clocking ratios.
Solution Approach 2:
The invention extracts unnecessary clock pulses from the clock signal before it reaches processing elements that require lower clock rates. By removing redundant clock pulses at the clock distribution level rather than using integer division, the system achieves arbitrary clock ratios while keeping data transfer paths simple and avoiding latency penalties.
2Use of energy by stationary object
If clock frequency is reduced for power saving, then power consumption decreases, but processing speed decreases
Solution Approach 1:
The clock deletion control unit dynamically adjusts the number of deleted clock pulses based on real-time processing requirements. When processing elements need to operate faster, fewer pulses are deleted; when power saving is prioritized, more pulses are deleted. This dynamic control allows the system to optimize the trade-off between power consumption and processing speed for each processing element independently.
Solution Approach 2:
The invention changes the clock frequency parameter delivered to each processing element by selectively deleting clock pulses. This allows continuous adjustment of clock frequency rather than being limited to fixed integer division ratios, enabling precise optimization of power consumption versus processing speed for each module based on its current workload and requirements.
3Ease of operation
If integer clock ratios are used, then data transfer simplicity is improved, but clock frequency adjustment flexibility deteriorates
Solution Approach 1:
The clock deletion control unit serves as an intermediary that transforms a master clock signal into customized clock signals with arbitrary ratios for different processing elements. By performing clock pulse deletion at this intermediate stage rather than relying on integer division at the data transfer interface, the system maintains simple synchronous data transfer while achieving flexible non-integer clock ratios.
Data Source
AI summary
A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.