Clock Pulse Masking for Cross-Frequency Communication Timing
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Solution Overview
Problem
Existing clock frequency divider circuits fail to maintain proper communication with circuits operating at different frequencies, leading to deteriorated communication performance, increased power consumption, and higher design costs due to the need for special clock transfer circuits and timing designs.
Innovation Solution
A clock frequency divider circuit that masks clock pulses at timings other than communication timings, using a mask control circuit to generate a mask timing signal and a mask restraint circuit to ensure clock pulses are not masked during communication, allowing for proper communication between circuits with different frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock pulses are masked to achieve frequency division, then frequency division ratio flexibility is improved, but communication reliability between circuits with different frequencies deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the masking behavior at different time points. Communication timing points are identified and protected from masking, while non-communication timing points are subject to masking for frequency division. This creates different functional qualities at different temporal locations, allowing both frequency division flexibility and communication reliability to coexist.
Solution Approach 2:
The patent uses preliminary action by pre-identifying communication timing points between circuits before the frequency division process. The communication timing signal is generated in advance to mark when data communication occurs, allowing the masking circuit to selectively preserve clock pulses at these predetermined timing points while masking others, thus ensuring communication reliability is maintained before the actual frequency division operation.
2Reliability
If special clock transfer circuits and timing designs are used to maintain communication, then communication reliability is improved, but device complexity and design cost increase
Solution Approach 1:
The patent applies universality by making the frequency division circuit itself perform the dual function of both frequency division and communication timing preservation. The mask control circuit uses the communication timing signal to control the masking operation, allowing the same circuit to achieve both frequency division and reliable communication without requiring separate dedicated clock transfer circuits or special timing design modules.
Solution Approach 2:
The patent merges the communication timing control function with the frequency division masking function. The mask control circuit combines the frequency division ratio control signal with the communication timing signal to generate a unified mask signal that simultaneously achieves frequency division and protects communication timing points, eliminating the need for separate special-purpose circuits.
3Reliability
If communication timing is preserved during frequency division, then communication performance is improved, but frequency division flexibility is restricted
Solution Approach 1:
The patent applies dynamics by making the masking operation adaptive rather than fixed. The mask control circuit dynamically adjusts which clock pulses are masked based on the combination of frequency division ratio settings and communication timing requirements. This dynamic control allows the system to flexibly achieve different frequency division ratios while automatically preserving communication timing points, maintaining both communication performance and frequency division flexibility.
Data Source
AI summary
A clock frequency divider circuit in accordance with the present invention is capable of generating a clock signal that makes it possible to perform an expected proper communication operation in communication with a circuit operating by a clock having a different frequency, and includes a mask control circuit 20 and a mask circuit 10. The mask control circuit 20 includes a mask timing signal generation circuit 22 that generates a mask timing signal 29 used to preferentially mask a clock pulse at a timing other than communication timings among M clock pulses of the input clock signal based on a communication timing signal 26, and a mask restraint circuit 62 that carries out a process to restrain masking of a clock pulse at a communication timing. The mask circuit 10 generates an output clock signal by masking clock pulses of an input clock signal according to a mask signal 50 generated by the mask control circuit.