Clock Pulse Omission for Power Supply Ripple Control
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Solution Overview
Problem
Processor cores with increasing speed demand varying current from the power supply, leading to current consumption fluctuations that cause power supply ripples, potentially malfunctioning the processing circuitry.
Innovation Solution
The processing circuitry estimates current consumption changes and adjusts its clock speed to reduce current fluctuations by preemptively slowing down operations during expected increases or decreases in current demand, using a current estimator and deletion module to omit clock pulses and thereby stabilize power supply output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor cores increase in speed to improve processing performance, then productivity increases, but current consumption increases causing power supply ripples that worsen system reliability
Solution Approach 1:
The system estimates future current consumption changes using a current estimator before they occur. When a significant change is predicted, clock pulses are preemptively deleted to prevent aggressive load steps on the power supply. This preliminary action allows the processor to maintain high speeds when possible while proactively preventing power supply instability.
Solution Approach 2:
The clock signal frequency is dynamically adjusted by selectively deleting clock pulses based on real-time current consumption patterns. The deletion module modifies the clock signal in response to estimated current changes, creating a dynamic balance between maintaining processing performance and ensuring power supply stability. This dynamic adjustment resolves the contradiction by adapting the operating frequency to current supply conditions.
2Productivity
If processor cores operate at high speed, then productivity improves, but current consumption fluctuations increase causing harmful power supply ripples
Solution Approach 1:
The system converts the potentially harmful effect of current consumption fluctuations into a useful signal for clock pulse deletion. The current estimator detects current consumption patterns, and when significant changes are anticipated, clock pulses are deleted to prevent power supply ripples. This transforms what would be harmful current variations into a control mechanism that maintains power supply stability while preserving processing throughput.
Solution Approach 2:
A feedback loop is established where the current estimator continuously monitors current consumption patterns and feeds this information to the deletion module. The deletion module adjusts the clock signal based on this feedback, creating a closed-loop control system that prevents power supply ripples while maintaining high processing speeds when conditions permit.
3Speed
If clock frequency is increased to improve processing speed, then productivity increases, but current consumption changes become more aggressive burdening the power supply
Solution Approach 1:
The system applies preliminary anti-action by deleting clock pulses before aggressive current consumption occurs. The current estimator predicts future current consumption changes, and when high current draw is anticipated, clock pulses are preemptively removed to counteract the potential harmful effect. This allows the processor to operate at high clock frequencies when conditions are favorable while preventing excessive current consumptionburdens on the power supply.
Data Source
AI summary
Various embodiments of the present disclosure are directed to managing load steps caused by processing circuitry. The processing circuitry may generate a series of clock pulses at an average clock period. The processing circuitry may estimate a current consumption of the processing circuitry at each clock pulse. Accordingly, a clock pulse from the series of clock pulses may be omitted when a change in the current consumption exceeds a predetermined threshold amount, thereby increasing the average clock period.