Clock Pulse Circuit Timing to Prevent Set-Reset Overlap
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Solution Overview
Problem
In clock pulse generation circuits, the simultaneous assertion of set and reset signals can lead to incorrect or inconsistent operation due to overlapping timing, which existing technologies fail to adequately address, especially in dense integrated circuits with varying timing constraints.
Innovation Solution
A clock pulse generation circuit is designed to prevent the set signal from being asserted when a reset signal is asserted, using a single pulse generator to generate the set signal based on the reset signal, thereby preventing override and ensuring consistent operation even when set and reset signals overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single pulse generator is used to generate both set and reset signals, then area and power consumption are reduced, but the risk of set and reset signals being asserted simultaneously increases
Solution Approach 1:
The patent applies preliminary action by generating the set signal based on the reset signal timing. The set signal is generated only after the reset signal assertion is anticipated and accounted for, ensuring that the set signal will not be asserted simultaneously with the reset signal. This preliminary timing arrangement prevents the harmful overlap condition before it can occur.
2Reliability
If separate set and reset pulse generators are used, then signal assertion reliability is improved, but area and power consumption increase
Solution Approach 1:
The patent merges the set and reset pulse generation functions into a single pulse generator circuit. By combining these functions and using the reset signal timing to control set signal generation, the circuit achieves the functionality of separate generators while reducing area and power consumption. The key is that the merging is done in a way that maintains reliability through the timing dependency relationship.
Solution Approach 2:
The single pulse generator is designed to perform multiple functions: generating both set and reset signals, and using the reset signal timing to control set signal generation. This multi-functionality allows the circuit to replace what would traditionally require separate dedicated generators, achieving area and power savings while maintaining the necessary signal integrity and timing control.
3Productivity
If clock signals are made faster to increase productivity, then productivity is improved, but the likelihood of timing overlaps between set and reset signals increases
Solution Approach 1:
The patent applies feedback by using the reset signal (or its indication) as an input to control the generation of the set signal. This creates a feedback loop where the timing of the reset signal directly influences when the set signal can be asserted. This feedback mechanism ensures that even at higher clock speeds, the set signal timing automatically adapts to prevent simultaneous assertion with the reset signal.
Data Source
AI summary
In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.