Clock Pulse Width Adjustment for 50% Duty Cycle Control
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Solution Overview
Problem
Existing clock circuits face challenges in accurately adjusting the duty cycle of clock signals due to structural asymmetry in P-type and N-type MOSFETs, leading to deviations and requiring a complex and time-consuming calibration process.
Innovation Solution
A clock circuit with a pulse width adjustment module, incorporating a sampling module and comparing module for feedback control, which adjusts the duty cycle of the input clock signal to lock it at 50%, using a simple structure that reduces circuit cost and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a traditional inverter or buffer circuit is used for clock signal generation, then the circuit structure is simple, but the duty cycle of the clock signal has deviation due to structural asymmetry of P-MOSFET and N-MOSFET
Solution Approach 1:
The patent implements a feedback mechanism where the clock signal is fed back through a sampling module that samples the voltage at specific points in the clock cycle. The sampled voltage is then compared with a reference voltage in a comparing module, and the comparison result is used to adjust the pulse width adjustment module, forming a closed-loop feedback system that automatically corrects duty cycle deviations
Solution Approach 2:
The patent changes the operating parameters of the MOSFETs by dynamically adjusting their gate voltages through the feedback control system. The pulse width adjustment module modifies the conduction time of the MOSFETs based on the comparison result, effectively changing their electrical characteristics to achieve precise duty cycle control without requiring physically symmetric transistors
2Manufacturing precision
If a pulse width adjustment circuit is added to correct the duty cycle, then the duty cycle accuracy is improved, but the circuit complexity increases and development schedule is delayed
Solution Approach 1:
The patent divides the clock circuit into distinct functional modules: a pulse width adjustment module for duty cycle control, a sampling module for voltage sampling at specific clock phases, and a comparing module for voltage comparison. This segmentation allows each module to perform its function independently with simple circuitry, reducing overall complexity while achieving precise duty cycle correction
Solution Approach 2:
The feedback control system makes the circuit self-adjusting by automatically detecting duty cycle deviations through voltage sampling and comparison, then self-correcting through the pulse width adjustment module. This eliminates the need for manual calibration and complex external adjustment mechanisms, simplifying the overall circuit design
3Manufacturing precision
If step-by-step calibration is used to adjust circuit parameters for precise duty cycle, then the duty cycle accuracy is improved, but the development time increases
Solution Approach 1:
The circuit performs automatic self-calibration through its feedback control mechanism. The sampling module continuously monitors the clock signal voltage, the comparing module detects deviations from the ideal 50% duty cycle, and the pulse width adjustment module automatically corrects the deviation. This eliminates the need for manual step-by-step calibration during development and operation, significantly reducing development time while maintaining high precision
Data Source
AI summary
A clock circuit has a clock input terminal, a first clock output terminal, and a second clock output terminal. The clock circuit includes a pulse width adjustment module, a sampling module, a comparing module, and a differential signal converting module. A differential input terminal is electrically connected to a pulse width output terminal of the pulse width adjustment module. A positive differential signal output terminal and a negative differential signal output terminal are electrically connected to the first clock output terminal of the clock circuit and the second clock output terminal to output two clock signals with a phase difference of 180 degrees, respectively. A second input terminal of the sampling module is electrically connected to the second clock output terminal.