Clock Frequency Ramp-Up for Power-On Voltage Stability
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Solution Overview
Problem
Computing devices face challenges in minimizing power consumption and chip area while maintaining performance, as existing power gating and clock gating techniques can lead to increased baseline power dissipation and power disturbances during transient operations.
Innovation Solution
A system comprising a voltage sensing module and a frequency adjustment module that senses supply voltage and adjusts the clock frequency of circuit blocks based on control signals, allowing for aggressive power gating and clock gating while using minimum supply voltage, thereby reducing power disturbances and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If aggressive power gating and clock gating are used to reduce power consumption, then power efficiency is improved, but power disturbances during transient operations increase and reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by ramping up the clock frequency gradually from a minimum frequency to the target frequency over a predetermined time period after power-on reset, rather than immediately setting it to the target frequency. This gradual frequency ramping prevents sudden power disturbances that would occur with aggressive immediate frequency setting, while still enabling power gating and clock gating to reduce overall power consumption.
2Use of energy by moving object
If minimum supply voltage is used to optimize power efficiency, then power consumption is reduced, but the ability to maintain performance during transient operations deteriorates
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable and time-dependent. The frequency adjustment module dynamically changes the clock frequency from a minimum frequency at power-on to a target frequency after a predetermined time period. This dynamic frequency adjustment allows the system to operate efficiently at minimum voltage initially, then transition to higher performance mode when voltage stabilizes, resolving the contradiction between power efficiency and performance.
3Productivity
If clock frequency is set to target frequency immediately after power-on reset, then productivity is improved, but power disturbances increase and reliability worsens
Solution Approach 1:
The patent applies preliminary action by implementing a delayed frequency setting mechanism. Instead of immediately setting the clock frequency to the target value after power-on reset, the system first operates at a minimum frequency for a predetermined time period to allow voltage stabilization, then transitions to the target frequency. This preliminary low-frequency operation phase prevents power disturbances while maintaining eventual productivity.
Data Source
AI summary
A system includes a voltage sensing module and a frequency adjustment module. The voltage sensing module is configured to sense a supply voltage of a circuit block, generate a first control signal when the supply voltage is less than or equal to a first voltage, and generate a second control signal when the supply voltage is within a predetermined range of a second voltage. The frequency adjustment module is configured to set a frequency of a clock signal supplied to the circuit block to less than a normal operating frequency of the circuit block when the supply voltage is initially supplied to the circuit block after a power on reset operation and the first control signal or the second control signal is received.