Clock Rate Management Circuit for Multi-Frequency Timer Monitoring
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Solution Overview
Problem
In mobile devices, using identical 32-bit timeout counters for various components is inefficient in terms of area utilization and power consumption, as the time of inactivity indicating component failure varies significantly across different components.
Innovation Solution
A prescalar counter generates a global time base signal, which is divided by a frequency divider into separate clock signals with different frequencies, allowing each timer to operate on a frequency tailored to its specific component's needs, thereby optimizing counter size and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If identical 32-bit timeout counters are used for all components, then uniform monitoring capability is achieved, but area utilization and power consumption become inefficient
Solution Approach 1:
The patent applies local quality by assigning different clock frequencies to different timers based on their specific monitoring requirements. Each timer receives a customized clock rate from the frequency divider, allowing components with longer inactivity periods to use lower-frequency clocks, thereby reducing power consumption locally where needed while maintaining uniform reliability across all monitored components.
2Reliability
If identical 32-bit timeout counters are used for all components, then uniform monitoring capability is achieved, but area utilization becomes inefficient
Solution Approach 1:
The patent enables variable counter sizes by providing different clock frequencies to different timers. This allows counters to be sized according to their actual needs - components with longer inactivity thresholds can use smaller counters operating at lower frequencies, optimizing area utilization while maintaining the necessary monitoring capability for each component.
3Device complexity
If a single clock rate is used for all timers, then simplified clock management is achieved, but efficiency in power consumption and area utilization deteriorates
Solution Approach 1:
The patent segments the clock management system by introducing a frequency divider that divides a master clock signal into multiple frequency-divided clock signals. This segmentation allows each timer to receive an appropriately sized clock frequency, reducing power consumption and area utilization for timers monitoring components with longer inactivity periods, while maintaining relatively simple overall system architecture.
4Device complexity
If a single clock rate is used for all timers, then simplified clock management is achieved, but efficiency in area utilization deteriorates
Solution Approach 1:
The frequency divider segments the clock signal into multiple frequency tiers, allowing timers to be sized and positioned according to their specific monitoring requirements. This enables smaller counters to be used for components with longer inactivity thresholds, optimizing area utilization while keeping the clock management system relatively simple through the use of a single master clock and divider circuit.
Data Source
AI summary
A prescalar counter may be configured to repeatedly increment once for each cycle of a clock signal at a first frequency and reset upon reaching a threshold counter value. The prescalar counter may also include toggling logic configured to generate a clock pulse of a global time base signal upon each reset of the prescalar counter. A frequency divider may be configured to divide the global time base signal into a plurality of separate clock signals with each of the separate clock signals having a different frequency. The frequency divider may also be configured to provide, to each of a plurality of timers, one of the separate clock signals.