Clock Ratio Controller for Dynamic Voltage Frequency Scaling
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Solution Overview
Problem
Dynamic voltage and frequency scaling in digital systems often results in loss of synchronization between system elements, disrupting communications and data exchange until resynchronization occurs.
Innovation Solution
A clock ratio controller is used to adjust the frequency of clock signals in digital systems without causing a loss of synchronization, by detecting alignments between clock signal edges and generating strobe signals to facilitate communication between digital circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic voltage and frequency scaling is implemented to reduce power consumption, then energy efficiency is improved, but synchronization between system elements is lost
Solution Approach 1:
The system performs preliminary actions by detecting clock alignments before frequency changes occur. The alignment detection mechanism identifies when clock edges coincide, and frequency transitions are scheduled to occur at these pre-detected alignment points, preventing synchronization loss before it can happen.
Solution Approach 2:
The system implements feedback by continuously monitoring clock signal alignments and using this information to control frequency scaling operations. The alignment detection output feeds back to the frequency scaler to determine when frequency changes should occur, creating a closed-loop control system that maintains synchronization while enabling power management.
2Speed
If clock frequency is dynamically adjusted to improve performance, then processing speed is improved, but synchronization between digital circuits is disrupted
Solution Approach 1:
The system detects clock alignments in advance and schedules frequency transitions to occur at these pre-identified alignment moments. This preliminary detection ensures that speed changes are coordinated with the timing of other digital circuits, maintaining synchronization while achieving performance optimization.
Solution Approach 2:
The system dynamically adjusts clock frequency based on real-time alignment conditions. The frequency scaler responds to changing operational requirements by modifying clock speeds, while the alignment detection mechanism ensures these dynamic changes occur at appropriate moments that preserve system-wide synchronization.
3Use of energy by moving object
If frequency scaling is implemented to manage power consumption, then energy efficiency is improved, but data communication between circuits is disrupted
Solution Approach 1:
The system performs preliminary alignment detection to identify safe transition points before frequency scaling occurs. By scheduling power management operations at these pre-detected alignment moments, the system prevents data communication disruptions while achieving energy efficiency goals.
Solution Approach 2:
The clock alignment detection mechanism acts as an intermediary between the frequency scaling controller and the data communication system. It mediates frequency changes by ensuring they occur only when alignment conditions are met, thereby protecting data communication integrity while enabling power management.
Data Source
AI summary
The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit.