Clock Signal Ratio Monitoring for Valid Counter Readings
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Solution Overview
Problem
Existing circuit arrangements fail to reliably detect and signal errors in clock signals, leading to invalid counter readings due to frequency fluctuations, which can result in faulty operations in applications like motor vehicle steering systems.
Innovation Solution
A method and device that utilize a signal processor to monitor the ratio between the clock signal frequency and a reference clock signal frequency, signaling errors if the ratio falls outside a predetermined range, ensuring that counter readings are validated only within a reliable frequency range, and incorporating periodic monitoring to maintain error-free operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal generator operates without continuous frequency monitoring, then the device complexity is reduced, but the reliability of counter readings deteriorates due to undetected frequency fluctuations
Solution Approach 1:
A signal processor is introduced as an intermediary component between the clock signal generator and the counter. This signal processor continuously monitors the frequency of the clock signal by counting clock cycles within a predetermined time period and comparing the measured frequency against expected frequency ranges, thereby ensuring counter reading reliability without requiring complex direct integration between the clock generator and counter units
Solution Approach 2:
The system implements feedback by continuously measuring the clock signal frequency and comparing it against predetermined frequency ranges. When the frequency falls outside the acceptable range, the system generates an error signal that invalidates subsequent counter readings, creating a closed-loop monitoring mechanism that maintains reliability through continuous verification
2Measurement precision
If frequency monitoring is implemented continuously, then the detection precision of clock errors is improved, but the use of energy increases due to continuous operation of the signal processor
Solution Approach 1:
Instead of continuous monitoring, the system performs frequency checks periodically at predetermined time intervals. The signal processor activates to measure the clock frequency, compares it against expected ranges, and then enters a low-power state until the next scheduled measurement, thereby maintaining detection precision while significantly reducing overall energy consumption compared to continuous monitoring
3Reliability
If the system validates all counter readings without frequency checking, then the productivity is maintained, but the reliability deteriorates due to inclusion of invalid counter readings from faulty clock signals
Solution Approach 1:
The system performs frequency validation checks before accepting counter readings. The signal processor verifies that the clock frequency is within the expected range prior to the counter units processing signals, thereby preventing invalid readings from being generated in the first place and eliminating the need for post-processing validation that would reduce productivity
Data Source
Figure 1
AI summary
The method involves synchronizing a circuit arrangement (ASIC) by a clock signal transmitter (LPO) and is formed dependent on a predetermined sensor signal (S-MR) to increment or decrement of a counter (CNT1,CNT2). The reference clock signal transmitter (RO) is switched on, such that a predetermined clock signal of the activated clock signal transmitter is controlled with a predetermined frequency. An independent claim is included for a device for operating a circuit arrangement with a clock signal transmitter and a reference clock signal transmitter.