Clock Distribution Chip Readiness Signaling for Deterministic Phase Setup
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Solution Overview
Problem
Existing clock distribution systems face challenges in determining when output clock signals are ready, leading to potential system errors or reduced performance due to unknown settling times for frequency and phase configurations, which is particularly problematic in systems with strict timing constraints like data converter and processor blocks supporting JESD204B signaling.
Innovation Solution
A clock distribution chip and method that includes a phase-locked loop, divider and phase control circuit, and controller to generate output clock signals with desired frequencies and phases, and provides a system ready signal to indicate when all output clock signals are ready, using finite state machines to control programmable dividers and phase control circuits to ensure deterministic phase relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is used to generate clock signals with desired frequencies and phases, then the clock signals achieve stable and low jitter performance, but the system cannot determine when the clock signals are ready, leading to unknown settling times
Solution Approach 1:
The patent implements a system ready circuit that monitors the state of the PLL and divider/phase control circuit, and provides a system ready signal that feeds back to indicate when output clock signals are ready. This feedback mechanism allows the system to know precisely when clock signals have settled to their desired frequencies and phases, resolving the uncertainty in settling time while maintaining the reliability benefits of PLL-based clock generation.
2Adaptability or versatility
If frequency division and phase control circuits are used to generate multiple clock signals, then the system can provide multiple low jitter clock signals, but it becomes difficult to track when all clock signals are configured correctly
Solution Approach 1:
The system ready circuit automatically monitors the configuration state of all divider and phase control circuits and generates the system ready signal without requiring external intervention. Each circuit element essentially serves itself by having its state automatically tracked and aggregated by the system ready circuit, which eliminates the need for complex external tracking mechanisms while supporting multiple clock signal generation.
3Reliability
If the system waits for unknown settling time before using clock signals, then potential errors are avoided, but system performance and productivity are reduced
Solution Approach 1:
The system ready circuit performs preliminary monitoring of clock signal configuration status and prepares the system ready signal in advance, indicating exactly when clock signals are ready for use. This allows the system to transition from clock signal generation to operational mode as quickly as possible without risking errors, thereby maximizing productivity while maintaining reliability through advance preparation and clear readiness indication.
Data Source
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AI summary
Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.