Clock Receiver Circuit Using Active Inductance for Low-Jitter SerDes
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Solution Overview
Problem
Existing clock signal receivers in serializer-deserializer (SerDes) communication links face issues with common mode voltage drift, high power consumption, significant circuit area usage, and clock signal latency, leading to operational problems and jitter.
Innovation Solution
Implementing a clock signal receiver circuit with an active inductance circuit, a common mode voltage source, and negative capacitance to stabilize common mode voltage, reduce power consumption, and minimize circuit area, while using a CML-to-CMOS converter for efficient signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock signal receiver circuits are used, then the circuit can process clock signals, but common mode voltage drift occurs leading to operational problems and jitter
Solution Approach 1:
A common mode voltage source is introduced as an intermediary component to actively control and stabilize the common mode voltage at the gates of the differential pair FETs. This mediator prevents common mode voltage drift by providing a stable reference, thereby eliminating operational problems and jitter without requiring changes to the core differential amplification mechanism.
2Stability of the object's composition
If passive inductors are used in the circuit, then inductance function is provided, but circuit area is significantly increased
Solution Approach 1:
Passive inductors are replaced with an active inductance circuit implemented using FETs (M54, M55) and associated capacitors. This substitution eliminates the need for large physical inductor components while maintaining the required inductance function through active circuitry, thereby significantly reducing the overall circuit area occupation.
3Productivity
If conventional circuit designs are used, then signal processing is performed, but power consumption is high
Solution Approach 1:
The circuit employs periodic switching action through the active inductance circuit and differential pair FETs to achieve signal processing. By using switched-capacitor techniques and periodic charging/discharging cycles, the circuit achieves the required signal processing functionality with reduced average power consumption compared to continuously operating conventional designs.
4Productivity
If conventional circuit designs are used, then signal processing is performed, but circuit area is significant
Solution Approach 1:
Multiple circuit functions are merged into integrated blocks: the active inductance circuit combines inductance generation with signal processing, the common mode voltage source integrates voltage control with biasing, and the differential pair FETs perform both amplification and switching functions. This functional merging reduces the overall circuit area by eliminating separate dedicated components for each function.
Data Source
AI summary
An apparatus, such as a clock signal receiver circuit, is disclosed. The apparatus includes a common mode voltage generator configured to generate a common mode voltage at an output; an input circuit comprising: a first field effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET; and a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET; and an active inductance circuit coupled in series with the first and second FETs between an upper voltage rail and a lower voltage rail, respectively.