Clock Receiver Calibration for Complementary Clock Phase Offset

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Solution Overview

Problem

Dynamic random access memories (DRAMs) face phase offset issues due to inconsistent duty cycles in complementary clocks, leading to distorted clock signals that affect internal circuit margins.

Innovation Solution

A clock receiver with a receiving unit, calibration unit, offset detector, bias generator, and phase adjustment unit that detects cross-point shifts and adjusts clock toggling using bias voltages to generate a main clock, thereby correcting phase offsets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a clock receiving unit receives complementary clocks with inconsistent duty cycles, then the clock signal is generated, but the cross point shifts causing phase offset and distorted clock signal

Engineering Contradiction:
Improveclock signal accuracyVSAvoidduty cycle consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by detecting the cross point shift before it affects the clock signal generation. The calibration unit detects whether the cross point has shifted from the expected position, and if so, generates a detected result that triggers premature adjustment of the clock signal to compensate for the duty cycle inconsistency, preventing the distorted clock signal from propagating to internal circuits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through the calibration unit that continuously monitors the cross point position of the complementary clocks. When a shift is detected, the system generates a detected result that feeds back to adjust the clock signal generation process, creating a closed-loop system that automatically compensates for duty cycle variations and maintains clock signal accuracy.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If the duty cycle of complementary clocks is inconsistent, then element mismatch or temperature effects occur, but this causes cross point shift and phase offset in the main clock

Engineering Contradiction:
Improveclock reception capabilityVSAvoidphase offset affecting margin
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies self-service by enabling the clock receiving unit to automatically detect and compensate for duty cycle inconsistencies without external intervention. The calibration unit self-monitors the cross point position and autonomously generates adjustment signals to correct phase offsets, allowing the system to adapt to manufacturing variations and temperature effects independently.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent utilizes parameter changes by adjusting the clock signal parameters (phase, timing) based on the detected cross point shift. The calibration unit modifies the clock signal generation parameters dynamically to compensate for duty cycle inconsistencies, thereby maintaining reliable operation despite variations in manufacturing processes or temperature conditions.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If cross point shift is detected, then calibration is performed, but this requires additional detection and adjustment mechanisms

Engineering Contradiction:
Improvecross point offset calibrationVSAvoidcalibration unit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies merging by integrating the calibration unit functionality into the existing clock receiving unit structure. The calibration unit detects cross point shifts and generates adjustment signals that are combined with the existing clock signal generation process, rather than adding a completely separate calibration system. This merging approach reduces overall device complexity while maintaining calibration capability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7724055B2Clock receivers
Publication Date: 2010.05.25 NAN YA TECH
  • US7724055B2 patent drawing
  • US7724055B2 patent drawing
  • US7724055B2 patent drawing

AI summary

A clock receiver is provided. A receiving unit receives a pair of complementary clocks and generates a first clock, and a calibration unit detects whether a cross point of the complementary clocks has shifted, generates a detected result and accordingly adjusts toggling of the first clock.