Clock Receiver Circuit With Common-Mode Control for Low Phase Noise
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Solution Overview
Problem
Existing clock receiving circuits in high-speed integrated circuits suffer from high phase noise and high power consumption due to the use of Current Mode Logic (CML) structures, which are susceptible to noise and mismatch, leading to reduced performance.
Innovation Solution
A clock receiving circuit with a common-mode voltage adjustment module, amplitude amplification module, and level conversion module, featuring n-type and p-type signal conversion units, p-type and n-type transistor differential pairs, and bias control units, to enhance transconductance and provide a large clock output swing at low power voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If Current Mode Logic (CML) structure is used to receive and amplify input clock, then amplification function is achieved, but phase noise increases and power consumption increases
Solution Approach 1:
The CML clock receiving circuit is divided into three independent modules: common-mode voltage adjustment module, amplitude amplification module, and level conversion module. Each module performs a specific function, allowing optimization of each segment separately to reduce overall phase noise while maintaining amplification capability and lowering power consumption.
Solution Approach 2:
A common-mode voltage adjustment module is introduced as an intermediary between the input clock and the amplitude amplification module. This module adjusts the common-mode voltage to an optimal level before amplification, preventing excessive power consumption and reducing phase noise generation in the amplification stage.
2Reliability
If CML structure is used, then clock signal amplification is achieved, but susceptibility to noise and mismatch increases
Solution Approach 1:
The common-mode voltage is adjusted in advance before the signal enters the amplification stage. By setting the optimal common-mode voltage level beforehand, the circuit operates in a more stable region that is less susceptible to noise and mismatch effects during amplification, reducing the need for excessive power consumption to maintain signal integrity.
Solution Approach 2:
The patent replaces the traditional CML amplification approach with a hybrid structure that uses differential pair amplification with explicit common-mode voltage control. This substitution allows for better noise immunity and mismatch tolerance while maintaining the necessary amplification function at lower power consumption.
3Speed
If high-speed clock transmission is implemented, then operating frequency increases, but signal attenuation increases and performance decreases
Solution Approach 1:
The patent optimizes the common-mode voltage parameter to match the specific requirements of high-speed clock transmission. By adjusting this voltage parameter to an optimal value, the circuit achieves better impedance matching and reduced signal attenuation at high operating frequencies, thereby maintaining signal integrity and performance.
Data Source
AI summary
Provided in the present disclosure is a clock receiving circuit. The clock receiving circuit comprises a common-mode voltage adjustment module, an amplitude amplification module and a level conversion module. The common-mode voltage adjustment module comprises an n-type signal conversion unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal conversion unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplification module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. The level conversion module is used for converting, into a CMOS level signal, a CML level signal which is output by the amplitude amplification circuit. Further provided in the present disclosure is an electronic device comprising the clock receiving circuit.